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參數(shù)資料
| 型號(hào)： | AS4DDR16M72-8/XT |
| 廠商： | AUSTIN SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 18/19頁 |
| 文件大?。?/td> | 363K |
| 代理商： | AS4DDR16M72-8/XT |
iiiiiPEM
PEM
1.2 G
1.2 Gbbbbb SDRAM-DDR
SDRAM-DDR
AS4DDR16M72PBG
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
Austin Semiconductor, Inc.
T0
T1
T2
T2n
T3
T3n
COMMAND
DQS
DQ
T0
T1
T2
T2n
T3
T3n
COMMAND
READ
NOP
CL = 2
CLK
READ
NOP
DQ
DQS
CLK
CL = 2.5
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
DATA
DON'T CARE
TRANSITIONING DATA
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
DLL
DS
Operating Mode
11
01
QFC#
Extended Mode
Register (Ex)
DLL
Enable
Disable
E0
0
1
Drive Strength
Normal
Reduced
E1
0
1
QFC# Function
Disabled
Reserved
E22
0
-
Operating Mode
Reserved
E2, E1, E0
Valid
-
E12
0
-
E10
0
-
E9
0
-
E8
0
-
E7
0
-
E6
0
-
E5
0
-
E4
0
-
E3
0
-
0
-
E11
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFE# function is not supported.
FIGURE 2 - CAS LATENCY
FIGURE 3 - EXTENDED MODE
REGISTER DEFINITION
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specified to
be SSTL2, Class II. The DDR SDRAM supports an option
for reduced drive. This option is intended for the support of
the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.
DLL ENABLE/DISABLE
The DLL must be enabled for normal operation. DLL enable
is required during power-up initialization and upon returning
to normal operation after having disabled the DLL for the
purpose of debug or evaluation. (When the device exits self
refresh mode, the DLL is enabled automatically.) Any time
the DLL is enabled, 200 clock cycles must occur before a
READ command can be issued.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of each
command.
DESELECT
The DESELECT function (CS# HiGH) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a
NOP to the selected DDR SDRAM (CS# is LOW). This
prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not
affected.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in
a particular bank for a subsequent access. The value on
the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0-12 selects the row. This row remains
active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE command
must be issued before opening a different row in the same
bank.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4DDR16M72PBG | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit |
| AS4DDR16M72PBG-10/ET | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
| AS4DDR16M72PBG-10/IT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
| AS4DDR16M72PBG-10/XT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
| AS4DDR16M72PBG-75/IT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
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