參數(shù)資料
型號(hào)： AS4DDR16M72-8/XT
廠商： AUSTIN SEMICONDUCTOR INC
元件分類： DRAM
英文描述： 16M X 72 DDR DRAM, 0.8 ns, PBGA219
封裝： 32 X 25 MM, PLASTIC, BGA-219
文件頁(yè)數(shù)： 5/19頁(yè)
文件大?。?/td> 363K
代理商： AS4DDR16M72-8/XT
iiiiiPEM
PEM
1.2 G
1.2 Gbbbbb SDRAM-DDR
SDRAM-DDR
AS4DDR16M72PBG
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
Austin Semiconductor, Inc.
ELECTRICAL
CHARACTERISTICS
AND
RECOMMENDED
AC
OPERATING
CHARACTERISTICS (NOTES 1-5, 14-17, 33)
Parameter
Symbol
-6, 333 [266] Mbps
-75, 266 [250] Mbps
Units
@CL=2.5 [CL=2]
Min
Max
Min
Max
Access window of DQs from CLK/CLK#
tAC
-0.70
+0.70
-0.75
+0.75
ns
CLK high-level width (30)
tCH
0.45
0.55
0.45
0.55
tCK
CLK low-level width (30)
tCL
0.45
0.55
0.45
0.55
tCK
Clock cycle time
CL=2.5 (45, 52)
tCK (2.5)
6
13
7.5
13
ns
CL=2 (45, 52)
tCK (2)
7.5
13
8
13
ns
DQ and DM input hold time relative to DQS (26, 31)
tDH
0.45
0.5
ns
DQ and DM input setup time relative to DQS (26,31)
tDS
0.45
0.5
ns
DQ and DM input pulse with (for each input) (31)
tDIPW
1.75
ns
Access window of DQS from CLK/CLK#
tDQSCK
-0.6
+0.6
-0.75
+0.75
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input high pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last valid, per group, per access (25,26)
tDQSQ
0.45
0.5
ns
Write command to first DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CLK rising - setup time
tDSS
0.2
tCK
DQS falling edge to CLK rising - hold time
tDSH
0.2
tCK
Half clock period (34)
tHP
tCH, tCL
ns
Data-out high-impedance window from CLK/CLK# (18, 42)
tHZ
+0.7
+0.75
ns
Data-out low-impedance window from CLK/CLK# (18, 43)
tLZ
-0.7
-0.75
ns
Address and control input hold time (fast slew rate) (14)
tIHF
0.75
0.9
ns
Address and control input setup time (fast slew rate) (14)
tISF
0.75
0.9
ns
Address and control input hold time (slow slew rate) (14)
tIHS
0.8
1.0
ns
Address and control input setup time (slow slew rate) (14)
tISS
0.8
1.0
ns
LOAD MODE REGISTER command cycle time
tMRD
12
15
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
tQH
tHP-tQHS
tHP
ns
-tQHS
Data hold skew factor
tQHS
0.55
1
ns
ACTIVE to PRECHARGE command (35)
tRAS
42
70,000
40
120,000
ns
ACTIVE to READ with Auto precharge command
tRAP
15
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
60
ns
AUTO REFRESH command period (50)
tRFC
72
75
ns
ACTIVE to READ or WRITE delay
tRCD
15
ns
PRECHARGE command period
tRP
15
ns
DQS read preamble (42)
tRPRE
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Active bank a to ACTIVE bank b command
tRRD
12
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time (20,21)
tWPRES
00
ns
DQS write postamble (19)
tWPST
0.4
0.6
0.4
0.6
tCK
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
11
tCK
Data valid output window (25)
NA
tQH - tDQSQ
tQH
ns
- tDQSQ
REFRESH to REFRESH command interval (Commercial & Industrial temp
tREFC
70.3
s
REFRESH to REFRESH command interval (Military temp only) (23)
tREFC
35
s
Average periodic refresh interval (Commercial & Industrial temp only) (23)
tREFI
7.8
s
Average periodic refresh interval (Military temp only) (23)
tREFI
3.9
s
Terminating voltage delay to Vcc (53)
tVTD
00
ns
Exit SELF REFRESH to non-READ command
tXSNR
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS4DDR16M72PBG 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit
AS4DDR16M72PBG-10/ET 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays
AS4DDR16M72PBG-10/IT 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays
AS4DDR16M72PBG-10/XT 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays
AS4DDR16M72PBG-75/IT 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays
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