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參數(shù)資料
| 型號： | AS4DDR16M72-8/XT |
| 廠商： | AUSTIN SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 363K |
| 代理商： | AS4DDR16M72-8/XT |
iiiiiPEM
PEM
1.2 G
1.2 Gbbbbb SDRAM-DDR
SDRAM-DDR
AS4DDR16M72PBG
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
Austin Semiconductor, Inc.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to zero,
and bits A0-A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command with
bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits
A0-A6 set to the desired values. Although not required,
JEDEC specifications recommend when a LOAD MODE
REGISTER command is issued to reset the DLL, it should
always be followed by a LOAD MODE REGISTER command
to select normal operating mode.
All other combinations of values for A7-A12 are reserved for
future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond those
controlled by the mode register; these additional functions
are DLL enable/disable, output drive strength, and QFC#.
These functions are controlled via the bits shown in Figure
3. The extended mode register is programmed via the LOAD
MODE REGISTER command to the mode register (with BA0
= 1 and BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a LOAD
MODE REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL.
The extended mode register must be loaded when all banks
are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subsequent
operation. Violating either of these requirements could result
in unspecified operation.
BA1
BA0
A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
Burst Length
BT
Operating Mode
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
0*
CAS Latency
* M14 and M13
mode register).
Mode Register (Mx)
M2 M1 M0
M3 = 0
M3 = 1
0
0 0
Reserved
0
0 1
2
0
1 0
4
0
1 1
8
1
0 0
Reserved
1
0 1
Reserved
1
1 0
Reserved
1
1 1
Reserved
Burst Length
0
1
Sequential
Interleaved
M3
Burst Type
CAS Latency
M6 M5 M4
Reserved
0
00
Reserved
0
1
2
0
1
0
Reserved
0
1
Reserved
1
0
Reserved
1
0
1
2.5
1
0
Reserved
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
0
id
M6-M0
M8
M7
M9
M10
0
1
0
--
-
M12
0
-
Valid
Val
M11
FIGURE 1 - MODE REGISTER DEFINITION
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AS4DDR16M72PBG | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit |
| AS4DDR16M72PBG-10/ET | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
| AS4DDR16M72PBG-10/IT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
| AS4DDR16M72PBG-10/XT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
| AS4DDR16M72PBG-75/IT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
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