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參數(shù)資料
| 型號： | AS4DDR16M72-8/XT |
| 廠商： | AUSTIN SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 363K |
| 代理商： | AS4DDR16M72-8/XT |
iiiiiPEM
PEM
1.2 G
1.2 Gbbbbb SDRAM-DDR
SDRAM-DDR
AS4DDR16M72PBG
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
Austin Semiconductor, Inc.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, and
an operating mode, as shown in Figure 3. The Mode Register
is programmed via the MODE REGISTER SET command
(with BA0 = 0 and BA1 = 0) and will retain the stored
information until it is programmed again or the device loses
power. (Except for bit A8 which is self clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must
wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecifi ed operation. Mode register bits A0-A2 specify
the burst length, A3 specifies the type of burst (sequential or
interleaved), A4-A6 specify the CAS latency, and A7-A12
specify the operating mode.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable, as
shown in Figure 3. The burst length determines the maximum
number of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 2, 4 or 8
locations are available for both the sequential and the
interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the
burst length is set to two; by A2-Ai when the burst length is
set to four (where Ai is the most significant column address
for a given configuration); and by A3-Ai when the burst length
is set to eight. The remaining (least signifi cant) address
bit(s) is (are) used to select the starting location within the
block. The programmed burst length applies to both READ
and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
A0
0
0-1
1
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
TABLE 1 - BURST DEFINITION
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block;
A0 selects the starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block;
A0-1 select the starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block;
A0-2 select the starting column within the block.
4. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
READ LATENCY
The READ latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first bit of output data. The latency can be set to 2 or 2.5
clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
SPEED
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
LATENCY=2
LATENCY=2.5
-10
75
100
-8
100
125
-75
100
133
-6
100
166
TABLE 2 - CAS LATENCY
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4DDR16M72PBG | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit |
| AS4DDR16M72PBG-10/ET | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
| AS4DDR16M72PBG-10/IT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
| AS4DDR16M72PBG-10/XT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
| AS4DDR16M72PBG-75/IT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
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