- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364674 > AMIS-53000 Frequency Agile Transceiver PDF資料下載
參數(shù)資料
| 型號： | AMIS-53000 |
| 英文描述： | Frequency Agile Transceiver |
| 中文描述： | 捷變頻收發(fā)器 |
| 文件頁數(shù)： | 34/99頁 |
| 文件大小： | 2638K |
| 代理商： | AMIS-53000 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
AMIS-53000
Frequency Agile Transceiver
Data Sheet
6.1.4.3.
Sequential Register Write
Figure 28: Sequential Control Data Read/Write with the I
2
C Interface
When setting the AMIS-53000 up for an application it sometimes is nice to write data to a number of registers one after the other. The
write control byte, register address and first data byte are transmitted to the AMIS-53000 in the same way as in a byte write. However,
instead of generating a stop condition, the master can continue to write register locations. Upon receipt of each word, the address is
internally incremented by ‘1’. If the master should transmit more words than the AMIS-53000 has address locations, the address will roll
over.
It is a similar approach to read a register value. The write control byte and register address are transmitted to the AMIS-53000 in the
same way as in a byte write. After receiving another acknowledge signal from the AMIS-53000, the master device will immediately
follow with another start sequence, however, the R/W bit is now set high telling the slave device that the master wants the contents of
the register (addressed with the write command) to be placed on the SDA bus line. After the 8 bits are read by the master, the master
acknowledges the reception. The AMIS-53000 will increment the register address and continue to output register values. After the last
register value is received by the master, the master does not respond with an acknowledge but sends the stop sequence.
6.1.4.4.
Current Address Read
The internal address counter maintains the last address addressed, incremented by ‘1’. If the last instruction received was to access
register N, the current address read operation will read the contents from register N+1. The timing for the current address read is to
send a start bit followed by the 7-bit device address, with the R/W bit set to one. The slave will acknowledge, after which the 8-bit
register contents will be transmitted. The master does not acknowledge the transmission, but does generate a stop bit.
34
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AMIS-53000-M | Frequency Agile Transceiver |
| AMIS-53050 | Frequency Agile Transceiver |
| AMIS-710650 | Color CIS Module Analog Video Output |
| AMIS-710650-A6 | Color CIS Module Analog Video Output |
| AMIS-710651 | Color CIS Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMIS53000/19608-001XT | 制造商:AMI Semiconductor 功能描述: 制造商:NTE Electronics 功能描述: |
| AMIS53000/SAMPLE | 制造商:AMI Semiconductor 功能描述: 制造商:NTE Electronics 功能描述: |
| AMIS-53000-I/A | 制造商:AMI 制造商全稱:AMI 功能描述:Frequency Agile Transceiver |
| AMIS-53000-M | 制造商:AMI 制造商全稱:AMI 功能描述:Frequency Agile Transceiver |
| AMIS-53050 | 制造商:ON Semiconductor 功能描述:WIRELESS LOW POWER TRANSC - 300-960MHZ, XTRA LOW RX PW, LQFP - Trays 制造商:ON Semiconductor 功能描述:WIRELESS LOW POWER TRANSC - 300-960MHZ, XTRA LOW RX PW, LQFP - Tape and Reel 制造商:ON Semiconductor 功能描述:WIRELESS LP TRANSC - 300-960MHZ, SPI INTERFACE:GANG XC, LQFP - Trays 制造商:ON Semiconductor 功能描述:WIRELESS LP TRANSC - 300-960MHZ, SPI INTERFACE:GANG XC, LQFP - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。