參數(shù)資料
型號: AMIS-53000
英文描述: Frequency Agile Transceiver
中文描述: 捷變頻收發(fā)器
文件頁數(shù): 28/99頁
文件大?。?/td> 2638K
代理商: AMIS-53000
AMIS-53000
Frequency Agile Transceiver
Data Sheet
28
6.0 User’s Guide
This user’s guide divides the control register description of the AMIS-53000 into functional areas; command register flow diagrams,
frequency generation, receiver, transmitter, idle, data/control interfaces, Burst transmit, and MICS features.
6.1 Control Serial Interface Bus Description
Table 11: Control Interface Physical Configuration
Clock
Data
Interface
Function
Pin
Source
Output
Input
Select
AMIS-53000
I
2
C
Control
SCLK
Master
SDATA
SDATA
None
Slave only
3-Wire
Control
SCLK
Master
SDATA
SDATA
SSN
Slave only
The AMIS-53000 employs two different control interfaces. Communication with the AMIS-53000 control registers is through either a
3-wire bus or through a 2-wire (with third line for control/status) I
C compatible bus. The state of the control bus is detected by the
AMIS-53000 at the first communication, I
C or 3-wire, and is set in that function (3-wire or I
C) as long as power remains applied to the
part.
3-wire control communication bus
I
C control communication bus
AMIS-53000 is always the slave
6.1.1. Control Interface Protocol
The AMIS-53000 control interface allows an external controller to write instructions to the registers of the AMIS-53000 and control the
functions of the AMIS-53000. The external controller can also read the registers and status of the AMIS-53000. The control interface
can be configured as a slave device in either a 2-wire I
C interface bus or a 3-wire serial interface.
Figure 21: Control I
2
C Protocol Format
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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