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參數(shù)資料
| 型號(hào)： | AM79C974 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | PCnetTM -的SCSI結(jié)合以太網(wǎng)和SCSI控制器PCI系統(tǒng) |
| 文件頁(yè)數(shù)： | 63/153頁(yè) |
| 文件大小： | 838K |
| 代理商： | AM79C974 |
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P R E L I M I N A R Y
AMD
63
Am79C974
the upper two bytes of the data bus will be undefined
since the byte mask will not be active for those bytes.
If DWIO mode has been invoked, then the BDP has a
width of 32 bits, hence, all BCR locations have 32 bits of
width and the upper two bytes of the data bus will be ac-
tive, as indicated by the byte mask. In this case, note
that the upper 16 bits of all BCR locations are reserved
and written as ZEROs and read as undefined. There-
fore, during BDP write operations in DWIO mode, the
upper 16 bits of all BCR locations should be written as
ZEROs.
RESET Register (S_RESET)
A read of the reset register creates an internal S_RE-
SET pulse in the Am79C974 controller. This read ac-
cess cycle must be 16 bits wide in WIO mode and 32 bits
wide in DWIO mode. The internal S_RESET pulse that
is generated by this access is different from both the as-
sertion of the hardware
RST
pin (H_RESET) and from
the assertion of the software STOP bit. Specifically, the
reset registers S_RESET will be the equivalent of the
assertion of the
RST
pin (H_RESET) assertion for all
CSR locations, but S_RESET will have no effect at all on
the BCR or PCI configuration space locations, and
S_RESET will not cause a deassertion of the
REQ
pin.
The NE2100 LANCE based family of Ethernet cards re-
quires that a write access to the reset register follows
each read access to the reset register. The Am79C974
controller does not have a similar requirement. The write
access is not required but it does not have any
harmfuleffects.
Write accesses to the reset register will have no effect
on the Am79C974 controller.
Note that a read access of the reset register will take
longer than the normal I/O access time of the
Am79C974 controller. This is because an internal
S_RESET pulse will be generated due to this access,
and the access will not be allowed to complete on the
system bus until the internal S_RESET operation has
been completed. This is to avoid the problem of allowing
a new I/O access to proceed while the S_RESET opera-
tion has not yet completed, which would result in errone-
ous data being returned by (or written into) the
Am79C974 controller. The length of a read of the Reset
register can be as long as 64 clock cycles.
Note that a read of the reset register will
not
cause a
deassertion of the
REQ
signal, if it happens to be active
at the time of the read of the reset register. The
REQ
sig-
nal will remain active until the
GNT
signal is asserted.
Following the read of the reset register, on the next clock
cycle after the
GNT
signal is asserted, the Am79C974
controller will deassert the
REQ
signal. No bus master
accesses will have been performed during this brief bus
ownership period.
Note that this behavior differs from that which occurs fol-
lowing the assertion of a minimum-width pulse on the
RST
pin (H_RESET). A
RST
pin assertion will cause the
REQ
signal to deassert within six clock cycles following
the assertion. In the
RST
pin case, the Am79C974 con-
troller will not wait for the assertion of the
GNT
signal be-
fore deasserting the
REQ
signal.
Vendor Specific Word
This I/O offset is reserved for use by the system de-
signer. The Am79C974 controller will not respond to ac-
cesses directed toward this offset. The Vendor Specific
Word is only available when the Am79C974 controller is
programmed to word I/O mode (DWIO = 0).
If more than one Vendor Specific Word is needed, it is
suggested that the VSW location should be divided into
a VSW Register Address Pointer (VSWRAP) at one lo-
cation (e.g. VSWRAP at byte location 18h or word loca-
tion 30h, depending upon DWIO state) and a VSW Data
Port (VSWDP) at the other location (e.g. VSWDP at byte
location 19h or word location 32h, depending upon
DWIO state). Alternatively, the system may capture
RAP data accesses in parallel with the Am79C974 con-
troller and therefore share the Am79C974 controller
RAP to allow expanded VSW space. Am79C974 con-
troller will not respond to access to the VSW I/O ad-
dress.
Reserved I/O Space
These locations are reserved for future use by AMD.
The Am79C974 controller does not respond to ac-
cesses directed toward these locations, but future AMD
products that are intended to be upward compatible with
the Am79C974 controller device may decode accesses
to these locations. Therefore, the system designer may
not utilize these I/O locations.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C974KCW | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C975 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C974KC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C974KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C974KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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