參數(shù)資料
型號(hào)： AM79C974
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
中文描述： PCnetTM -的SCSI結(jié)合以太網(wǎng)和SCSI控制器PCI系統(tǒng)
文件頁(yè)數(shù)： 19/153頁(yè)
文件大?。?/td> 838K
代理商： AM79C974
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P R E L I M I N A R Y
AMD
19
Am79C974
PIN DESCRIPTION
PCI Bus Interface
AD[31:00]
Address and Data
Input/Output, Active High
These signals are multiplexed on the same PCI pins.
During the first clock of a transaction AD[31:00] contain
the physical byte address (32 bits). During the subse-
quent clocks AD[31:00] contain data. Byte ordering is lit-
tle endian by default. AD[07:00] are defined as least
significant byte and AD[31:24] are defined as the most
significant byte. For FIFO data transfers, the PCnet-
SCSI controller can be programmed for big endian byte
ordering. See CSR3, bit 2 (BSWP) for more details.
During the address phase of the transaction, when the
PCnet-SCSI controller is a bus master, AD[31:2] will ad-
dress the active DWORD (double-word). The PCnet-
SCSI controller always drives AD[1:0] to ‘00’ during the
address phase indicating linear burst order. When the
PCnet-SCSI controller is not a bus master, the
AD[31:00] lines are continuously monitored to deter-
mine if an address match exists for I/O slave transfers.
During the data phase of the transaction, AD[31:00] are
driven by the PCnet-SCSI controller when performing
bus master writes and slave read operations. Data on
AD[31:00] is latched by the PCnet-SCSI controller when
performing bus master reads and slave write
operations.
When
RST
is active, AD[31:0] are inputs for NAND tree
testing.
C/
BE
[3:0]
Bus Command and Byte Enables
Input/Output, Active Low
These signals are multiplexed on the same PCI pins.
During the address phase of the transaction, C/
BE
[3:0]
define the bus command. During the data phase
C/
BE
[3:0] are used as Byte Enables. The Byte Enables
define which physical byte lanes carry meaningful data.
C/
BE
0 applies to byte 0 (AD[07:00]) and C/
BE
3 applies
to byte 3 (AD[31:24]). The function of the Byte Enables
is independent of the byte ordering mode (CSR3, bit 2).
When
RST
is active, C/
BE
[3:0] are inputs for NAND tree
testing.
CLK
Clock
Input
This signal provides timing for all the transactions on the
PCI bus and all PCI devices on the bus including the
PCnet-SCSI controller. All bus signals are sampled on
the rising edge of CLK and all parameters are defined
with respect to this edge. The PCnet-SCSI controller op-
erates over a range of 0 to 33 MHz.
When
RST
is active, CLK is an input for NAND tree
testing.
DEVSEL
Device Select
Input/Output, Active Low
This signal when actively driven by the PCnet-SCSI
controller as a slave device signals to the master device
that the PCnet-SCSI controller has decoded its address
as the target of the current access. As an input it indi-
cates whether any device on the bus has been selected.
When
RST
is active,
DEVSEL
is an input for NAND tree
testing.
FRAME
Cycle Frame
Input/Output, Active Low
This signal is driven by the PCnet-SCSI controller when
it is the bus master to indicate the beginning and dura-
tion of the access.
FRAME
is asserted to indicate a bus
transaction is beginning.
FRAME
is asserted while data
transfers continue.
FRAME
is deasserted when the
transaction is in the final data phase.
When
RST
is active,
FRAME
is an input for NAND tree
testing.
GNTA
Bus Grant
Input, Active Low
This signal indicates that the access to the bus has been
granted to the Am79C974’s SCSI controller.
The Am79C974 controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts
GNTA
without an active
REQA
from the Am79C974 controller,
the controller will actively drive the AD[31:00], C/
BE
[3:0], and PAR lines.
When
RST
is active,
GNTA
is an input for NAND tree
testing.
GNTB
Bus Grant
Input, Active Low
This signal indicates that the access to the bus has been
granted to the Am79C974’s Ethernet controller. The
Am79C974 controller supports bus parking. When the
PCI bus is idle and the system arbiter asserts
GNTB
without an active
REQB
from the Am79C974 controller,
the controller will actively drive the AD, C/
BE
and PAR
lines.
相關(guān)PDF資料
PDF描述
AM79C974KCW PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
AM79C975 PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
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AM79C973KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C974KC 制造商:Advanced Micro Devices 功能描述:
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AM79C974KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
AM79C975 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
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