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參數(shù)資料
| 型號(hào)： | AM79C973 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY |
| 文件頁數(shù)： | 88/304頁 |
| 文件大小： | 2092K |
| 代理商： | AM79C973 |
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Am79C973/Am79C975
P R E L I M I N A R Y
The Am79C973/Am79C975 device implements the
transmit and receive Auto-Negotiation algorithm as de-
fined in IEEE 802.3u, Section 28. The Auto-Negotiation
algorithm uses a burst of link pulses called Fast Link
Pulses (FLPs). The burst of link pulses are spaced be-
tween 55 and 140 μs so as to be ignored by the stan-
dard 10BASE-T algorithm. The FLP burst conveys
information about the abilities of the sending device.
The receiver can accept and decode an FLP burst to
learn the abilities of the sending device. The link pulses
transmitted conform to the standard 10BASE-T tem-
plate. The device can perform auto-negotiation with re-
verse polarity link pulses.
The Am79C973/Am79C975 device uses the Auto-Ne-
gotiation algorithm to select the type connection to be
established according to the following priority:
100BASE-TX full duplex, 100BASE-T4, 100BASE-TX
half-duplex, 10BASE-T full duplex, 10BASE-T half-du-
plex. The Am79C973/Am79C975 device does not sup-
port 100BASE-T4 connections.
The Auto-Negotiation algorithm is initiated when one or
the following events occurs: Auto-Negotiation enable
bit is set, or reset, or soft reset, or transition to link fail
state (when Auto-Negotiation enable bit is set), or Auto-
Negotiation restart bit is set. The result of the Auto-Ne-
gotiation process can be read from the status register
(Summary Status Register, ANR24).
The Am79C973/Am79C975 device supports Parallel
Detection for remote legacy devices which do not sup-
port the Auto-Negotiation algorithm. In the case that a
100BASE-TX only device is connected to the remote
end, the Am79C973/Am79C975 device will see scram-
bled idle symbols and establish a 100BASE-TX only
connection. If NLPs are seen, the Am79C973/
Am79C975 device will establish a 10BASE-T connec-
tion.
By default, the link partner must be at least 10BASE-T
half-duplex capable. The Am79C973/Am79C975 con-
troller can automatically negotiate with the network and
yield the highest performance possible without soft-
ware support. See the section on
Network Port Man-
ager
for more details.
Auto-Negotiation goes further by providing a message-
based communication scheme called,
Next Pages
, be-
fore connecting to the Link Partner.
This feature is not
supported in the Am79C973/Am79C975 device unless
the DANAS (BCR32, bit 10) is selected.
Soft Reset Function
The PHY Control Register (ANR0) incorporates the
soft reset function (bit 15). It is a read/write register and
is self-clearing. Writing a 1 to this bit causes a soft re-
set. When read, the register returns a 1 if the soft reset
is still being performed; otherwise, it is cleared to 0.
Note that the register can be polled to verify that the
soft reset has terminated
. Under normal operating con-
ditions, soft reset will be finished in 150 clock cycles.
Soft reset only resets the 10/100 PHY unit registers to
default values (some register bits retain their previous
values). Refer to the individual registers for values after
a soft reset. Soft reset does not reset the PDX block nor
the management interface.
Soft reset is required when changing the value of the
SDISSCR (scrambling/descrambling) bit. After soft
reset, the register will retain the previous value written.
External Address Detection Interface
The EADI is provided to allow external address filtering
and to provide a Receive Frame Tag word for propri-
etary routing information. It is selected by setting the
EADISEL bit in BCR2 to 1. This feature is typically uti-
lized by terminal servers, bridges and/or router prod-
ucts. The EADI interface can be used in conjunction
with external logic to capture the packet destination ad-
dress as it arrives at the Am79C973/Am79C975 con-
troller, to compare the captured address with a table of
stored addresses or identifiers, and then to determine
whether or not the Am79C973/Am79C975 controller
should accept the packet.
If an address match is detected by comparison with ei-
ther the Physical Address or Logical Address Filter reg-
isters contained within the Am79C973/Am79C975
controller or the frame is of the type 'Broadcast', then
the frame will be accepted regardless of the condition
of EAR. When the EADISEL bit of BCR2 is set to 1 and
the Am79C973/Am79C975 controller is programmed
to promiscuous mode (PROM bit of the Mode Register
is set to 1), then all incoming frames will be accepted,
regardless of any activity on the EAR pin.
Internal address match is disabled when PROM
(CSR15, bit 15) is cleared to 0, DRCVBC (CSR15, bit
14) and DRCVPA (CSR15, bit 13) are set to 1, and the
Logical Address Filter registers (CSR8 to CSR11) are
programmed to all zeros.
When the EADISEL bit of BCR2 is set to 1 and internal
address match is disabled, then all incoming frames
will be accepted by the Am79C973/Am79C975 control-
Table 10. Auto-Negotiation Capabilities
Network Speed
Physical Network Type
200 Mbps
100BASE-X, Full Duplex
100 Mbps
100BASE-T4, Half Duplex
100 Mbps
100BASE-X, Half Duplex
20 Mbps
10BASE-T, Full Duplex
10 Mbps
10BASE-T, Half Duplex
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