參數(shù)資料
型號(hào)： AM79C973
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY
文件頁(yè)數(shù)： 106/304頁(yè)
文件大小： 2092K
代理商： AM79C973
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106
Am79C973/Am79C975
P R E L I M I N A R Y
When the Am79C973/Am79C975 controller detects a
Magic Packet frame, it sets the MPMAT bit (CSR116,
bit 5), the MPINT bit (CSR5, bit 4), and the
PME_STATUS bit (PMCSR, bit 15). The setting of the
MPMAT bit will also cause the RWU pin to be asserted
and if the PME_EN or the PME_EN_OVR bits are set,
then the PME will be asserted as well. If IENA (CSR0,
bit 6) and MPINTE (CSR5, bit 3) are set to 1, INTA will
be asserted. Any one of the four LED pins can be pro-
grammed to indicate that a Magic Packet frame has
been received. MPSE (BCR4-7, bit 9) must be set to 1
to enable that function.
Note:
The polarity of the LED pin can be programmed
to be active HIGH by setting LEDPOL (BCR4-7, bit 14)
to 1.
Once a Magic Packet frame is detected, the
Am79C973/Am79C975 controller will discard the frame
internally, but will not resume normal transmit and re-
ceive operations until PG is asserted or MPEN is
cleared. Once both of these events has occurred, indi-
cating that the system has detected the Magic Packet
and is awake, the controller will continue polling receive
and transmit descriptor rings where it left off. It is not
necessary to re-initialize the device. If the part is re-ini-
tialized, then the descriptor locations will be reset and
the Am79C973/Am79C975 controller will not start
where it left off.
If magic packet mode is disabled by the assertion of
PG, then in order to immediately re-enable Magic
Packet mode, the PG pin must remain deasserted for
at least 200 ns before it is reasserted. If Magic Packet
mode is disabled by clearing MPEN bit, then it may be
immediately re-enabled by setting MPEN back to 1.
The PCI bus interface clock (CLK) is not required to be
running while the device is operating in Magic Packet
mode. Either of the INTA, the LED pins, RWU or the
PME signal may be used to indicate the receipt of a
Magic Packet frame when the CLK is stopped. If the
system wishes to stop the CLK, it will do so after en-
abling the Magic Packet mode.
CAUTION:
To prevent unwanted interrupts from other
active parts of the Am79C973/Am79C975 controller,
care must be taken to mask all likely interruptible
events during Magic Packet mode. An example would
be the interrupts from the Media Independent Interface,
which could occur while the device is in Magic Packet
mode.
IEEE 1149.1 (1990) Test Access Port
Interface
An IEEE 1149.1-compatible boundary scan Test Ac-
cess Port is provided for board-level continuity test and
diagnostics. All digital input, output, and input/output
pins are tested. The following paragraphs summarize
the IEEE 1149.1-compatible test functions imple-
mented in the Am79C973/Am79C975 controller.
Boundary Scan Circuit
The boundary scan test circuit requires four pins (TCK,
TMS, TDI, and TDO), defined as the Test Access Port
(TAP). It includes a finite state machine (FSM), an in-
struction register, a data register array, and a power-on
reset circuit. Internal pull-up resistors are provided for
the TDI, TCK, and TMS pins.
TAP Finite State Machine
The TAP engine is a 16-state finite state machine
(FSM), driven by the Test Clock (TCK), and the Test
Mode Select (TMS) pins. An independent power-on
reset circuit is provided to ensure that the FSM is in the
TEST_LOGIC_RESET state at power-up. Therefore,
the TRST is not provided. The FSM is also reset when
TMS and TDI are high for five TCK periods.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST, and SAMPLE instructions), three
additional instructions (IDCODE, TRIBYP, and SET-
BYP) are provided to further ease board-level testing.
All unused instruction codes are reserved. See Table
16 for a summary of supported instructions.
Instruction Register and Decoding Logic
After the TAP FSM is reset, the IDCODE instruction is
always invoked. The decoding logic gives signals to con-
trol the data flow in the Data registers according to the
current instruction.
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two
stages. A flip-flop and a latch are used for the Serial
Shift Stage and the Parallel Output Stage, respectively.
Table 16. IEEE 1149.1 Supported Instruction
Summary
Instruction
Name
EXTEST
Instruction
Code
0000
Description
External Test
ID Code
Inspection
Sample
Boundary
Force Float
Control
Boundary To
1/0
Bypass Scan
Mode
Test
Selected
Data
Register
BSR
IDCODE
0001
Normal
ID REG
SAMPLE
0010
Normal
BSR
TRIBYP
0011
Normal
Bypass
SETBYP
0100
Test
Bypass
BYPASS
1111
Normal
Bypass
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