參數(shù)資料
型號(hào)： AM79C973
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY
文件頁(yè)數(shù)： 117/304頁(yè)
文件大?。?/td> 2092K
代理商： AM79C973
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Am79C973/Am79C975
117
P R E L I M I N A R Y
any specific register-level programming interfaces for
network devices. The value of this register is 00h.
The PCI Programming Interface register is located at
offset 09h in the PCI Configuration Space. It is read only.
PCI Sub-Class Register
Offset 0Ah
The PCI Sub-Class register is an 8-bit register that iden-
tifies specifically the function of the Am79C973/
Am79C975 controller. The value of this register is 00h
which identifies the Am79C973/Am79C975 device as
an Ethernet controller.
The PCI Sub-Class register is located at offset 0Ah in
the PCI Configuration Space. It is read only.
PCI Base-Class Register
Offset 0Bh
The PCI Base-Class register is an 8-bit register that
broadly classifies the function of the Am79C973/
Am79C975 controller. The value of this register is 02h
which classifies the Am79C973/Am79C975 device as
a network controller.
The PCI Base-Class register is located at offset 0Bh in
the PCI Configuration Space. It is read only.
PCI Latency Timer Register
Offset 0Dh
The PCI Latency Timer register is an 8-bit register that
specifies the minimum guaranteed time the Am79C973/
Am79C975 controller will control the bus once it starts
its bus mastership period. The time is measured in clock
cycles. Every time the Am79C973/Am79C975 control-
ler asserts FRAME at the beginning of a bus mastership
period, it will copy the value of the PCI Latency Timer
register into a counter and start counting down. The
counter will freeze at 0. When the system arbiter re-
moves GNT while the counter is non-zero, the
Am79C973/Am79C975 controller will continue with its
data transfers. It will only release the bus when the
counter has reached 0.
The PCI Latency Timer is only significant in burst trans-
actions, where FRAME stays asserted until the last data
phase. In a non-burst transaction, FRAME is only as-
serted during the address phase. The internal latency
counter will be cleared and suspended while FRAME is
deasserted.
All eight bits of the PCI Latency Timer register are pro-
grammable. The host should read the Am79C973/
Am79C975 PCI MIN_GNT and PCI MAX_LAT registers
to determine the latency requirements for the device
and then initialize the Latency Timer register with an
appropriate value.
The PCI Latency Timer register is located at offset 0Dh
in the PCI Configuration Space. It is read and written by
the host. The PCI Latency Timer register is cleared by
H_RESET and is not effected by S_RESET or by setting
the STOP bit.
PCI Header Type Register
Offset 0Eh
The PCI Header Type register is an 8-bit register that
describes the format of the PCI Configuration Space
locations 10h to 3Ch and that identifies a device to be
single or multi-function. The PCI Header Type register
is located at address 0Eh in the PCI Configuration
Space. It is read only.
Bit
Name
Description
7
FUNCT
Single-function/multi-function de-
vice. Read as zero; write opera-
tions
have
no
Am79C973/Am79C975 controller
is a single function device.
effect.
The
6-0
LAYOUT
PCI configuration space layout.
Read as zeros; write operations
have no effect. The layout of the
PCI configuration space loca-
tions 10h to 3Ch is as shown in
the table at the beginning of this
section.
PCI I/O Base Address Register
Offset 10h
The PCI I/O Base Address register is a 32-bit register
that determines the location of the Am79C973/
Am79C975 I/O resources in all of I/O space. It is located
at offset 10h in the PCI Configuration Space.
Bit
Name
Description
31-5
IOBASE
I/O base address most significant
27 bits. These bits are written by
the host to specify the location of
the Am79C973/Am79C975 I/O
resources in all of I/O space. IO-
BASE must be written with a valid
address before the Am79C973/
Am79C975 controller slave I/O
mode is turned on by setting the
IOEN bit (PCI Command register,
bit 0).
When
Am79C975 controller is enabled
for I/O mode (IOEN is set), it
monitors the PCI bus for a valid I/
O command. If the value on
AD[31:5] during the address
phase of the cycles matches the
value
of
IOBASE,
Am79C973/Am79C975 controller
the
Am79C973/
the
相關(guān)PDF資料
PDF描述
AM79C973KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C976 PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C973/75 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF)
AM79C973/AM79C975 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am79C973/Am79C975 - PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973AVC\\W 制造商:Advanced Micro Devices 功能描述:
AM79C973AVC\W 制造商:Advanced Micro Devices 功能描述:
AM79C973BKC 制造商:Advanced Micro Devices 功能描述:79C973BKC
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