參數(shù)資料
型號(hào)： AM79C973
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY
文件頁(yè)數(shù)： 30/304頁(yè)
文件大小： 2092K
代理商： AM79C973
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30
Am79C973/Am79C975
P R E L I M I N A R Y
INTA
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: EXDINT, IDON, MERR,
MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT,
TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MRE-
INT, and STINT. Each status flag has either a mask or
an enable bit which allows for suppression of INTA as-
sertion. Table 1 shows the flag descriptions. By default
INTA is an open-drain output. For applications that
need a high-active edge-sensitive interrupt signal, the
INTA pin can be configured for this mode by setting IN-
TLEVEL (BCR2, bit 7) to 1.
Output
When RST is active, INTA is the output for NAND tree
testing
.
IRDY
Initiator Ready
IRDY indicates the ability of the initiator of the transac-
tion to complete the current data phase. IRDY is used
in conjunction with TRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
Input/Output
When the Am79C973/Am79C975 controller is a bus
master, it asserts IRDY during all write data phases to
indicate that valid data is present on AD[31:0]. During
all read data phases, the device asserts IRDY to indi-
cate that it is ready to accept the data.
When the Am79C973/Am79C975 controller is the tar-
get of a transaction, it checks IRDY during all write data
phases to determine if valid data is present on
AD[31:0]. During all read data phases, the device
checks IRDY to determine if the initiator is ready to ac-
cept the data.
When RST is active, IRDY is an input for NAND tree
testing
.
PAR
Parity
Parity is even parity across AD[31:0] and C/BE[3:0].
When the Am79C973/Am79C975 controller is a bus
master, it generates parity during the address and write
data phases. It checks parity during read data phases.
When the Am79C973/Am79C975 controller operates
in slave mode, it checks parity during every address
phase. When it is the target of a cycle, it checks parity
during write data phases and it generates parity during
read data phases.
Input/Output
When RST is active, PAR is an input for NAND tree
testing
.
.
PERR
Parity Error
During any slave write transaction and any master read
transaction, the Am79C973/Am79C975 controller as-
serts PERR when it detects a data parity error and re-
porting of the error is enabled by setting PERREN (PCI
Command register, bit 6) to 1. During any master write
transaction, the Am79C973/Am79C975 controller
monitors PERR to see if the target reports a data parity
error.
Input/Output
When RST is active, PERR is an input for NAND tree
testing
.
Table 1. Interrupt Flags
Name
Description
Excessive
Deferral
Initialization
Done
Memory Error
Missed Frame
Missed Frame
Count Over-
flow
Magic Packet
Interrupt
Receive
Collision Count
Overflow
Receive
Interrupt
System Error
Transmit
Interrupt
Transmit Start
User Interrupt
MII
Management
Command
Complete
Interrupt
MII PHY Detect
Transition
Interrupt
MII Auto-Poll
Interrupt
MII
Management
Frame Read
Error Interrupt
Software Timer
Interrupt
Mask Bit
Interrupt Bit
EXDINT
CSR5, bit 6
CSR5, bit 7
IDON
CSR3, bit 8
CSR0, bit 8
MERR
MISS
CSR3, bit 11
CSR3, bit 12
CSR0, bit 11
CSR0, bit 12
MFCO
CSR4, bit 8
CSR4, bit 9
MPINT
CSR5, bit 3
CSR5, bit 4
RCVCCO
CSR4, bit 4
CSR4, bit 5
RINT
CSR3, bit 10
CSR0, bit 10
SINT
CSR5, bit 10
CSR5, bit 11
TINT
CSR3, bit 9
CSR0, bit 9
TXSTRT
UINT
CSR4, bit 2
CSR4, bit 7
CSR4, bit 3
CSR4, bit 6
MCCINT
CSR7, bit 4
CSR7, bit 5
MPDTINT
CSR7, bit 0
CSR7, bit 1
MAPINT
CSR7, bit 6
CSR7, bit 7
MREINT
CSR7, bit 8
CSR7, bit 9
STINT
CSR7, bit 10
CSR7, bit 11
相關(guān)PDF資料
PDF描述
AM79C973KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C976 PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
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AM79C973/AM79C975 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am79C973/Am79C975 - PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973AVC\\W 制造商:Advanced Micro Devices 功能描述:
AM79C973AVC\W 制造商:Advanced Micro Devices 功能描述:
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