參數(shù)資料
型號(hào)： AM79C973
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY
文件頁(yè)數(shù)： 34/304頁(yè)
文件大?。?/td> 2092K
代理商： AM79C973
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34
Am79C973/Am79C975
P R E L I M I N A R Y
EBDA[15:8]
Expansion Bus Data/Address [15:8]
Output
When EROMCS is asserted low, EBDA[15:8] contain
address bits [15:8] for boot device accesses.
Input/
The EBDA[15:8] signals are driven to a constant level
to conserve power while no access on the Expansion
Bus is being performed.
Note:
EBDA[15:8] pins are multiplexed with the
TXD[3:0], TX_EN, MDIO, CRS, and COL pins.
EBD[7:0]
Expansion Bus Data [7:0]
The EBD[7:0] pins provide data bits [7:0] for EPROM/
FLASH accesses. The EBD[7:0] signals are internally
forced to a constant level to conserve power while no
access on the Expansion Bus is being performed.
Input/Output
Note:
EBD[7:0] pins are multiplexed with the
RXD[3:0], RX_DV, RX_CLK, RX_ER, and TX_CLK
pins.
EROMCS
Expansion ROM Chip Select
EROMCS serves as the chip select for the boot device.
It is asserted low during the data phases of boot device
accesses.
AS_EBOE
Address Strobe/Expansion Bus
Output Enable
AS_EBOE functions as the address strobe for the
upper address bits on the EBUA_EBA[7:0] pins and as
the output enable for the Expansion Bus.
Output
Output
As an address strobe, a rising edge on AS_EBOE is
supplied at the beginning of boot device accesses. This
rising edge provides a clock edge for a
‘
374 D-type
edge-triggered flip-flop which must store the upper ad-
dress byte during Expansion Bus accesses for
EPROM/Flash.
AS_EBOE is asserted active LOW during boot device
read operations on the expansion bus and is deas-
serted during boot device write operations.
EBWE
Expansion Bus Write Enable
EBWE provides the write enable for write accesses to
the Flash device.
EBCLK
Expansion Bus Clock
EBCLK may be used as the fundamental clock to drive
the Expansion Bus and internal SRAM access cycles.
The actual internal clock used to drive the Expansion
Bus cycles depends on the values of the EBCS and
Output
Input
CLK_FAC settings in BCR27. Refer to the SRAM Inter-
face Bandwidth Requirements section for details on de-
termining the required EBCLK frequency. If a clock
source other than the EBCLK pin is programmed
(BCR27, bits 5:3) to be used to run the Expansion Bus
interface, this input should be tied to VDD through a 4.7
kW resistor.
EBCLK is not used to drive the bus interface, internal
buffer management unit, or the network functions.
Media Independent Interface (MII)
TX_CLK
Transmit Clock
TX_CLK is a continuous clock input that provides the
timing reference for the transfer of the TX_EN,
TXD[3:0], and TX_ER signals out of the Am79C973/
Am79C975 device. TX_CLK must provide a nibble rate
clock (25% of the network data rate). Hence, an MII
transceiver operating at 10 Mbps must provide a
TX_CLK frequency of 2.5 MHz and an MII transceiver
operating at 100 Mbps must provide a TX_CLK fre-
quency of 25 MHz.
Input
Note:
The TX_CLK pin is multiplexed with the EBD7
pin.
TXD[3:0]
Transmit Data
TXD[3:0] is the nibble-wide MII transmit data bus. Valid
data is generated on TXD[3:0] on every TX_CLK rising
edge while TX_EN is asserted. While TX_EN is de-
asserted, TXD[3:0] values are driven to a 0. TXD[3:0]
transitions synchronous to TX_CLK rising edges.
Output
Note:
The TXD[3:0] pins are multiplexed with the
EBDA[11:8] pins.
TX_EN
Transmit Enable
TX_EN indicates when the Am79C973/Am79C975 de-
vice is presenting valid transmit nibbles on the MII.
While TX_EN is asserted, the Am79C973/Am79C975
device generates TXD[3:0] and TX_ER on TX_CLK ris-
ing edges. TX_EN is asserted with the first nibble of
preamble and remains asserted throughout the dura-
tion of a packet until it is deasserted prior to the first
TX_CLK following the final nibble of the frame. TX_EN
transitions synchronous to TX_CLK rising edges.
Output
Note:
The TX_EN pin is multiplexed with the EBDA12
pin.
TX_ER
Transmit Error
TX_ER is an output that, if asserted while TX_EN is as-
serted, instructs the MII PHY device connected to the
Am79C973/Am79C975 device to transmit a code
Output
相關(guān)PDF資料
PDF描述
AM79C973KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C975VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C976 PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C973/75 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF)
AM79C973/AM79C975 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am79C973/Am79C975 - PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973AVC\\W 制造商:Advanced Micro Devices 功能描述:
AM79C973AVC\W 制造商:Advanced Micro Devices 功能描述:
AM79C973BKC 制造商:Advanced Micro Devices 功能描述:79C973BKC
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