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參數(shù)資料
| 型號： | AM79C973 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY |
| 文件頁數(shù)： | 290/304頁 |
| 文件大小： | 2092K |
| 代理商： | AM79C973 |
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290
Am79C973/Am79C975
P R E L I M I N A R Y
modified buffer point into the third descriptor, then
the controller will complete the frame in buffer num-
ber 2 and then skip the then unowned third buffer. In
this case, the Am79C973 controller will not have
had the opportunity to RESET the ENP bit in this
descriptor, and it is possible that the software left
this bit as ENP = 1 from the last time through the
ring. Therefore, the software must treat the location
as a
don
’
t care.
The rule is, after finding ENP = 1 (or
ERR = 1) in descriptor number 2, the software must
ignore ENP bits until it finds the next STP = 1.
Example 3
: Assume that instead of the expected
1060 byte frame, a 100 byte frame arrives, because
there was an error in the network, or because this is
the last frame in a file transmission sequence, or
perhaps because it is an acknowledge frame.
*
Same as note in example 2 above, except that in this
case, it is very unlikely that the driver can respond to
the interrupt and get the pointer from the application
before the Am79C973 controller has completed its poll
of the next descriptors. This means that for almost all
occurrences of this case, the Am79C973 controller will
not find the OWN bit set for this descriptor and, there-
fore, the ENP bit will almost always contain the old
value, since the Am79C973 controller will not have had
an opportunity to modify it.
**Note that even though the Am79C973 controller will
write a ZERO to this ENP location, the software should
treat the location as a don
’
t care, since after finding the
ENP = 1 in descriptor number 2, the software should ig-
nore ENP bits until it finds the next STP = 1.
Buffer Size Tuning
For maximum performance, buffer sizes should be ad-
justed depending upon the expected frame size and
the values of the interrupt latency and application call
latency. The best driver code will minimize the CPU uti-
lization while also minimizing the latency from frame
end on the network to the frame sent to application
from driver (frame latency). These objectives are aimed
at increasing throughput on the network while decreas-
ing CPU utilization.
Note:
The buffer sizes in the ring may be altered at any
time that the CPU has ownership of the corresponding
descriptor. The best choice for buffer sizes will maxi-
mize the time that the driver is swapped out, while min-
imizing the time from the last byte written by the
Am79C973 controller to the time that the data is
passed from the driver to the application. In the dia-
gram, this corresponds to maximizing S0, while mini-
mizing the time between C9 and S8. (the timeline
happens to show a minimal time from C9 to S8.)
Note:
By increasing the size of buffer number 1, we in-
crease the value of S0. However, when we increase the
size of buffer number 1, we also increase the value of
S4. If the size of buffer number 1 is too large, then the
driver will not have enough time to perform tasks S2,
S3, S4, S5, and S6. The result is that there will be delay
from the execution of task C9 until the execution of task
S8. A perfectly timed system will have the values for S5
and S7 at a minimum.
An average increase in performance can be achieved,
if the general guidelines of buffer sizes in Figure 2 is fol-
lowed. However, as was noted earlier, the correct sizing
for buffers will depend upon the expected message
size. There are two problems with relating expected
message size with the correct buffer sizing:
1. Message sizes cannot always be accurately pre-
dicted, since a single application may expect differ-
ent message sizes at different times. Therefore, the
buffer sizes chosen will not always maximize
throughput.
2. Within a single application, message sizes might be
somewhat predictable, but when the same driver is
to be shared with multiple applications, there may
not be a common predictable message size.
Additional problems occur when trying to define the
correct sizing because the correct size also depends
upon the interrupt latency, which may vary from system
to system, depending upon both the hardware and the
software installed in each system.
Descriptor
Number
1
2
3
Before the Frame Arrives
OWN
STP
1
1
0
After the Frame Arrives
OWN
0
0
0
Comments (After
Frame Arrival)
Bytes 1-800
Discarded buffer
Discarded buffer
Controller
’
s current
location
Not yet used
Not yet used
Net yet used
ENP
a
x
X
X
STP
1
0
0
ENP
b
0
0**
1
0
0
4
1
1
X
1
1
X
5
6
1
0
1
0
0
1
X
X
X
1
0
1
0
0
1
X
X
X
etc.
a.
& b.ENP or ERR
.
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| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C973/75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF) |
| AM79C973/AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am79C973/Am79C975 - PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973AVC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C973AVC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C973BKC | 制造商:Advanced Micro Devices 功能描述:79C973BKC |
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