296
Am79C973/Am79C975
P R E L I M I N A R Y
CONNECTION DIAGRAM (PQL176)
Am79C973 . . . . . . . . . . . . . . . . . . . . . . . .19
CONNECTION DIAGRAM (PQL176)
Am79C975 . . . . . . . . . . . . . . . . . . . . . . . .21
CONNECTION DIAGRAM (PQR160) . . .18
CONNECTION DIAGRAM (PQR160)
Am79C975 . . . . . . . . . . . . . . . . . . . . . . . .20
Control and Status Registers . . .123, 214, 259
Control Register (Register 0) . . . . . . . . . . .274
CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
CSR0
Am79C972 Controller Status and
Control Register . . . . . . . . . . . . . . .123
CSR1
Initialization Block Address 0 . . . . . . .126
CSR10
Logical Address Filter 2 . . . . . . . . . . .137
CSR100
Bus Timeout . . . . . . . . . . . . . . . . . . . . .153
CSR11
Logical Address Filter 3 . . . . . . . . . . .137
CSR112
Missed Frame Count . . . . . . . . . . . . . .154
CSR114
Receive Collision Count . . . . . . . . . . .154
CSR116
OnNow Power Mode Register . . . . . . .154
CSR12
Physical Address Register 0 . . . . . . . .137
CSR122
Advanced Feature Control . . . . . . . . . .156
CSR124
Test Register 1 . . . . . . . . . . . . . . . . . . .156
CSR125
MAC Enhanced Configuration
Control . . . . . . . . . . . . . . . . . . . . . .156
CSR13
Physical Address Register 1 . . . . . . . .137
CSR14
Physical Address Register 2 . . . . . . . .137
CSR15
Mode . . . . . . . . . . . . . . . . . . . . . . . . . .138
CSR16
Initialization Block Address
Lower . . . . . . . . . . . . . . . . . . . . . . .139
CSR17
Initialization Block Address
Upper . . . . . . . . . . . . . . . . . . . . . . .140
CSR18
Current Receive Buffer Address
Lower . . . . . . . . . . . . . . . . . . . . . . . . . .140
CSR19
Current Receive Buffer Address
Upper . . . . . . . . . . . . . . . . . . . . . . .140
CSR2
Initialization Block Address 1 . . . . . . .126
CSR20
Current Transmit Buffer Address
Lower . . . . . . . . . . . . . . . . . . . . . . .140
CSR21
Current Transmit Buffer Address
Upper . . . . . . . . . . . . . . . . . . . . . . .140
CSR22
Next Receive Buffer Address
Lower . . . . . . . . . . . . . . . . . . . . . . .140
CSR23
Next Receive Buffer Address
Upper . . . . . . . . . . . . . . . . . . . . . . .140
CSR24
Base Address of Receive Ring
Lower . . . . . . . . . . . . . . . . . . . . . . .141
CSR25
Base Address of Receive Ring
Upper . . . . . . . . . . . . . . . . . . . . . . .141
CSR26
Next Receive Descriptor Address
Lower . . . . . . . . . . . . . . . . . . . . . . .141
CSR27
Next Receive Descriptor Address
Upper . . . . . . . . . . . . . . . . . . . . . . .141
CSR28
Current Receive Descriptor Address
Lower . . . . . . . . . . . . . . . . . . . . . . .141
CSR29
Current Receive Descriptor Address
Upper . . . . . . . . . . . . . . . . . . . . . . .141
CSR3
Interrupt Masks and Deferral
Control . . . . . . . . . . . . . . . . . . . . . .126
CSR30
Base Address of Transmit Ring
Lower . . . . . . . . . . . . . . . . . . . . . . .141
CSR31
Base Address of Transmit Ring