參數(shù)資料
型號(hào): AM79C973
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述: PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY
文件頁(yè)數(shù): 188/304頁(yè)
文件大小: 2092K
代理商: AM79C973
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188
Am79C973/Am79C975
P R E L I M I N A R Y
identifies the manufacturer of the
Am79C973/Am79C975 control-
ler. AMD
s Vendor ID is 1022h.
Note that this Vendor ID is not the
same as the Manufacturer ID in
CSR88 and CSR89. The Vendor
ID is assigned by the PCI Special
Interest Group.
The Vendor ID is not normally
programmable,
Am79C973/Am79C975 controller
allows this due to legacy operat-
ing systems that do not look at
the PCI Subsystem Vendor ID
and the Vendor ID to uniquely
identify the add-in board or sub-
system that the Am79C973/
Am79C975 controller is used in.
but
the
Note: If the operating system
or the network operating sys-
tem supports PCI Subsystem
Vendor ID and Subsystem ID,
use those to identify the add-in
board or subsystem and pro-
gram the VID with the default
value of 1022h
.
VID is aliased to the PCI configu-
ration space register Vendor ID
(offset 00h).
Read accessible always. VID is
read only. Write operations are
ignored. VID is set to 1022h by
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
BCR36: PCI Power Management Capabilities (PMC)
Alias Register
Note:
This register is an alias of the PMC register
located at offset 42h of the PCI Configuration Space.
Since PMC register is read only, BCR36 provides a
means of programming it through the EEPROM. The
contents of this register are copied into the PMC regis-
ter. For the definition of the bits in this register, refer to
the PMC register definition. Bits 15-0 in this register are
programmable through the EEPROM. Read accessible
always. Read only. Cleared by H_RESET and is not af-
fected by S_RESET or setting the STOP bit.
BCR37: PCI DATA Register Zero (DATA0) Alias
Register
Note:
This register is an alias of the DATA register and
also of the DATA_SCALE field of the PMCSR register.
Since these two are read only, BCR37 provides a
means of programming them indirectly. The contents of
this register are copied into the corresponding fields
pointed with the DATA_SEL field set to zero. Bits 15-0
in this register are programmable through the EE-
PROM.
Bit
Name
Description
15-10 RES
Reserved locations. Written as
zeros and read as undefined.
9-8
D0_SCALE
These bits correspond to the
DATA_SCALE
PMCSR (offset Register 44 of the
PCI configuration space, bits 14-
13). Refer to the description of
DATA_SCALE for the meaning of
this field.
field
of
the
Read
D0_SCALE is read only. Cleared
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
accessible
always.
7-0
DATA0
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
Read accessible always. DATA0
is
read
only.
H_RESET and is not affected by
S_RESET or setting the STOP bit
Cleared
by
BCR38: PCI DATA Register One (DATA1) Alias
Register
Note:
This register is an alias of the DATA register and
also of the DATA_SCALE field of the PMCSR register.
Since these two are read only, BCR38 provides a
means of programming them through the EEPROM.
The contents of this register are copied into the corre-
sponding fields pointed with the DATA_SEL field set to
one. Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
15-10 RES
Reserved locations. Written as
zeros and read as undefined.
9-8
D1_SCALE
These bits correspond to the
DATA_SCALE field of the PMC-
SR (offset Register 44 of the PCI
configuration space, bits 14-13).
Refer to the description of
DATA_SCALE for the meaning of
this field.
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