參數(shù)資料
型號(hào)： AM79C970AKCW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝： PLASTIC, QFP-132
文件頁(yè)數(shù)： 90/219頁(yè)
文件大小： 1065K
代理商： AM79C970AKCW
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)當(dāng)前第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)
AMD
P R E L I M I N A R Y
90
Am79C970A
the EADISEL bit of BCR2 is set to ONE and the PCnet-
PCI II controller is programmed to promiscuous mode
(PROM bit of the Mode Register is set to ONE), then all
incoming frames will be accepted, regardless of any ac-
tivity on the
EAR
pin.
Internal address match is disabled when PROM
(CSR15, bit 15) is cleared to ZERO, DRCVBC (CSR15,
bit 14) and DRCVPA (CSR15, bit 13) are set to ONE and
the Logical Address Filter registers (CSR8 to CSR11)
are programmed to all ZEROs.
When the EADISEL bit of BCR2 is set to ONE and inter-
nal address match is disabled, then all incoming frames
will be accepted by the PCnet-PCI II controller, unless
the
EAR
pin becomes active during the first 64 bytes of
the frame (excluding preamble and SFD). This allows
external address lookup logic approximately 58 byte
times after the last destination address bit is available to
generate the
EAR
signal, assuming that the PCnet-PCI
II controller is not configured to accept runt packets. The
EADI logic only samples
EAR
from 2 bit times after SFD
until 512 bit times (64 bytes) after SFD. The frame will be
accepted if
EAR
has not been asserted during this win-
dow. If Runt Packet Accept (CSR124, bit 3) is enabled,
then the
EAR
signal must be generated prior to the re-
ceive message completion, if frame rejection is to be
guaranteed. Runt packet sizes could be as short as 12
byte times (assuming 6 bytes for source address, 2
bytes for length, no data, 4 bytes for FCS) after the last
bit of the destination address is available.
EAR
must
have a pulse width of at least 110 ns.
Note that when the PCnet-PCI II controller is operating
in full-duplex mode or runt packet accept is turned on
(CSR124, bit 3) the Receive FIFO Watermark (CSR80,
bits 13–12) must be programmed to 64 (01b) or 128
(10b) to allow the full window of 512 bit times after SFD
for the assertion of
EAR
. If the watermark was pro-
grammed to 16 (00b), receive FIFO DMA could start be-
fore
EAR
is asserted to reject the frame.
The EADI outputs continue to provide data throughout
the reception of a frame. This allows the external logic
to capture frame header information to determine
protocol type, inter-networking information, and other
useful data.
The EADI interface will operate as long as the STRT bit
in CSR0 is set, even if the receiver and/or transmitter
are disabled by software (DTX and DRX bits in CSR15
are set). This configuration is useful as a semi-power-
down mode in that the PCnet-PCI II controller will not
perform any power-consuming DMA operations. How-
ever, external circuitry can still respond to control
frames on the network to facilitate remote node control.
The table below summarizes the operation of the
EADI interface:
Table 11. EADI Operations
PROM
EAR
Required Timing
Received Messages
1
X
No timing requirements
All received frames
0
1
No timing requirements
All received frames
0
0
Low for 110 ns during the window from
2 bits after SFD to 512 bits after SFD
PCnet-PCI II controller internal physical
address and logical address filter
matches and broadcast frames
Expansion ROM Interface
The Expansion ROM is an 8-bit ROM connected to the
PCnet-PCI II controller Expansion ROM Data bus
(ERD). It can be of up to 64 Kbytes in size. The Expan-
sion ROM Address bus (ERA) is 8 bits wide. An external
latch is required to store the upper 8 bits of the 16-bit ad-
dress to the ROM. All ERA outputs are forced to a con-
stant level to conserve power while no access to the
Expansion ROM is performed.
EROE
is asserted during the Expansion ROM read op-
eration. This signal can be used to control the
OE
input
of the ROM. In an application that does not use the GPSI
port, EROE can be left unconnected and the
OE
input of
the ROM can be tied to ground to always enable the
ROM data outputs. The
CE
input of the ROM can either
be tied to ground or it can also be connected to EROE.
The signal ERACLK is provided to strobe the upper 8
bits of the address into an external latch. The timing rela-
tion of ERACLK to ERA is such that both ’373 (transpar-
ent latch) and ’374 (D flip-flop) types of address latch
can be used.
相關(guān)PDF資料
PDF描述
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970 PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C971VCW PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970AVC 制造商:Advanced Micro Devices 功能描述:
AM79C970AVC\\W 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:
AM79C970AVC\W 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:AMD 功能描述:
AM79C970AVC-G 制造商:Rochester Electronics LLC 功能描述:
AM79C970AVCW 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*