P R E L I M I N A R Y
AMD
119
Am79C970A
9
MFCO
Missed Frame Counter Overflow
is set by the PCnet-PCI II
controller when the Missed
Frame
Counter
wraps around.
When MFCO is set,
INTA
is as-
serted if IENA is ONE and the
mask bit MFCOM is ZERO.
Read/Write accessible always.
MFCO is cleared by the host by
writing a ONE. Writing a ZERO
has no effect. MFCO is cleared
by H_RESET, S_RESET or by
setting the STOP bit.
When the value 01h has been
programmed into the SWSTYLE
register (BCR20, bits 7–0) for
ILACC (Am79C900) compatibil-
ity, then this bit has no meaning
and PCnet-PCI II controller will
never set the value of this bit
to ONE.
Missed Frame Counter Overflow
Mask. If MFCOM is set, the
MFCO bit will be masked and un-
able to set the INTR bit.
Read/Write accessible always.
MFCOM is set to ONE by
H_RESET or S_RESET and is
unaffected
by
STOP bit.
When the value 01h has
been programmed into the
SWSTYLE register (BCR20, bits
7–0) for ILACC (Am79C900)
compatibility, then this bit has no
meaning and PCnet-PCI II con-
troller will clear the value of this
bit to ZERO.
User
Interrupt
UINTCMD can be used by the
host to generate an interrupt un-
related to any network activity.
When UINTCMD is set,
INTA
is
asserted if IENA is set to ONE.
UINTCMD
will
internally after the PCnet-PCI II
controller has set UINT to ONE.
Read/Write accessible always.
UINTCMD
is
H_RESET or S_RESET or by
setting the STOP bit.
User Interrupt. UINT is set by the
PCnet-PCI II controller after the
host has issued a user interrupt
command by setting UINTCMD
(CSR4, bit 7) to ONE.
Read/Write accessible always.
UINT is cleared by the host by
writing a ONE. Writing a ZERO
(CSR112)
8
MFCOM
setting
the
7
UINTCMD
Command.
be
cleared
cleared
by
6
UINT
has no effect. UINT is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
Receive Collision Counter Over-
flow is set by the PCnet-PCI II
controller when the Receive
Collision
Counter
wraps around.
When RCVCCO is set,
INTA
is
asserted if IENA is ONE and the
mask bit RCVCCOM is ZERO.
Read/Write accessible always.
RCVCCO is cleared by the host
by writing a ONE. Writing a
ZERO has no effect. RCVCCO is
cleared by H_RESET, S_RESET
or by setting the STOP bit.
When the value 01h has been
programmed into the SWSTYLE
register (BCR20, bits 7–0) for
ILACC (Am79C900) compatibil-
ity, then this bit has no meaning
and PCnet-PCI II controller will
never set the value of this bit
to ONE.
Receive Collision Counter Over-
flow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
RCVCCOM is set to ONE by
H_RESET or S_RESET and is
unaffected
by
STOP bit.
When the value 01h has been
programmed into the SWSTYLE
register (BCR20, bits 7–0) for
ILACC (Am79C900) compatibil-
ity, then this bit has no meaning
and PCnet-PCI II controller will
clear the value of this bit
to ZERO.
Transmit Start status is set by the
PCnet-PCI II controller whenever
it begins transmission of a frame.
When TXSTRT is set,
INTA
is as-
serted if IENA is ONE and the
mask bit TXSTRTM is ZERO.
Read/Write accessible always.
TXSTRT is cleared by the host by
writing a ONE. Writing a ZERO
has no effect. TXSTRT is cleared
by H_RESET, S_RESET or by
setting the STOP bit.
Transmit
Start
TXSTRTM is set, the TXSTRT bit
will be masked and unable to set
the INTR bit.
5
RCVCCO
(CSR114)
4
RCVCCOM
setting
the
3
TXSTRT
2
TXSTRTM
Mask.
If