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參數(shù)資料
| 型號： | AM79C970AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 212/219頁 |
| 文件大?。?/td> | 1065K |
| 代理商： | AM79C970AKCW |
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AMD
D-8
Am79C970A
An average increase in performance can be achieved if
the general guidelines of buffer sizes in figure 2 is fol-
lowed. However, as was noted earlier, the correct sizing
for buffers will depend upon the expected message size.
There are two problems with relating expected message
size with the correct buffer sizing:
1. Message sizes cannot always be accurately pre-
dicted, since a single application may expect differ-
ent message sizes at different times, therefore, the
buffer sizes chosen will not always maximize
throughput.
2. Within a single application, message sizes might
be somewhat predictable, but when the same
driver is to be shared with multiple applications,
there may not be a common predictable message
size.
Additional problems occur when trying to define the cor-
rect sizing because the correct size also depends upon
the interrupt latency, which may vary from system to
system, depending upon both the hardware and the
software installed in each system.
In order to deal with the unpredictable nature of the mes-
sage size, the driver can implement a self tuning mecha-
nism that examines the amount of time spent in tasks S5
and S7 as such: while the driver is polling for each de-
scriptor, it could count the number of poll operations per-
formed and then adjust the number 1 buffer size to a
larger value, by adding “t” bytes to the buffer count, if the
number of poll operations was greater than “x”. If fewer
than “x” poll operations were needed for each of S5 and
S7, then the software should adjust the buffer size to a
smaller value by, subtracting “y” bytes from the buffer
count. Experiments with such a tuning mechanism must
be performed to determine the best values for “X”
and “y”.
Note whenever the size of buffer number 1 is adjusted,
buffer sizes for buffer number 2 and buffer 3 should also
be adjusted.
In some systems, the typical mix of receive frames on a
network for a client application consists mostly of large
data frames, with very few small frames. In this case, for
maximum efficiency of buffer sizing, when a frame ar-
rives under a certain size limit, the driver should not ad-
just the buffer sizes in response to the short frame.
An Alternative LAPP Flow—the TWO Interrupt
Method
An alternative to the above suggested flow is to use two
interrupts, one at the start of the receive frame and the
other at the end of the receive frame, instead of just look-
ing for the SRP interrupt as was described above. This
alternative attempts to reduce the amount of time that
the software wastes while polling for descriptor own bits.
This time would then be available for other CPU tasks. It
also minimizes the amount of time the CPU needs for
data copying. This savings can be applied to other
CPU tasks.
The time from the end of frame arrival on the wire to de-
livery of the frame to the application is labeled as frame
latency. For the one-interrupt method, frame latency is
minimized, while CPU utilization increases. For the two-
interrupt method, frame latency becomes greater, while
CPU utilization decreases.
Note that some of the CPU time that can be applied to
non-Ethernet tasks is used for task switching in the
CPU. One task switch is required to swap a non-Ether-
net task into the CPU (after S7A) and a second task
switch is needed to swap the Ethernet driver back in
again (at S8A). If the time needed to perform these task
switches exceeds the time saved by not polling descrip-
tors, then there is a net loss in performance with this
method. Therefore, the LAPP method implemented
should be carefully chosen.
相關PDF資料 |
PDF描述 |
|---|---|
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AVC\\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVC\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:AMD 功能描述: |
| AM79C970AVC-G | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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