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參數(shù)資料
| 型號(hào)： | AM79C970AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 73/219頁 |
| 文件大?。?/td> | 1065K |
| 代理商： | AM79C970AKCW |
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P R E L I M I N A R Y
AMD
73
Am79C970A
Error Detection
The MAC engine provides several facilities which report
and recover from errors on the medium. In addition, it
protects the network from gross errors due to inability of
the host to keep pace with the MAC engine activity.
On completion of transmission, the following transmit
status is available in the appropriate Transmit Message
Descriptor (TMD) and Control and Status Register
(CSR) areas:
I
The number of transmission retry attempts (ONE,
MORE, RTRY, and TRC).
I
Whether the MAC engine had to Defer (DEF) due to
channel activity.
I
Excessive deferral (EXDEF), indicating that the
transmitter has experienced Excessive Deferral on
this transmit frame, where Excessive Deferral is de-
fined in ISO 8802-3 (IEEE/ANSI 802.3).
I
Loss of Carrier (LCAR), indicating that there was an
interruption in the ability of the MAC engine to
monitor its own transmission. Repeated LCAR er-
rors indicate a potentially faulty transceiver or net-
work connection.
I
Late Collision (LCOL) indicates that the transmission
suffered a collision after the slot time. This is indica-
tive of a badly configured network. Late collisions
should not occur in a normal operating network.
I
Collision Error (CERR) indicates that the transceiver
did not respond with an SQE Test message within
the first 4
μ
s after a transmission was completed.
This may be due to a failed transceiver,
disconnected or faulty transceiver drop cable, or the
fact the transceiver does not support this feature (or
it is disabled).
In addition to the reporting of network errors, the MAC
engine will also attempt to prevent the creation of any
network error due to the inability of the host to service
the MAC engine. During transmission, if the host fails to
keep the transmit FIFO filled sufficiently, causing an un-
derflow, the MAC engine will guarantee the message is
either sent as a runt packet (which will be deleted by the
receiving station) or has an invalid FCS (which will also
cause the receiver to reject the message).
The status of each receive message is available in the
appropriate Receive Message Descriptor (RMD) and
CSR areas. All received frames are passed to the host
regardless of any error. The FRAM error will only be re-
ported if an FCS error is detected and there are a non
integral number of bytes in the message.
During the reception, the FCS is generated on every se-
rial bit (including the dribbling bits) coming from the ca-
ble, although the internally saved FCS value is only
updated on the eighth bit (on each byte boundary). The
MAC engine will ignore up to 7 additional bits at the end
of a message (dribbling bits), which can occur under
normal network operating conditions. The framing error
is reported to the user as follows:
I
If the number of dribbling bits are 1 to 7 and there is
no FCS error, then there is no Framing error
(FRAM = 0).
I
If the number of dribbling bits are 1 to 7 and there is a
FCS error, then there is also a Framing error
(FRAM = 1).
I
If the number of dribbling bits is ZERO, then there is
no Framing error. There may or may not be a
FCS error.
I
If the number of dribbling bits is EIGHT, then there is
no Framing error. FCS error will be reported and the
receive message count will indicated one extra byte.
Counters are provided to report the Receive Collision
Count and Runt Packet Count, for network statistics and
utilization calculations.
Note that if the MAC engine detects a received frame
which has a 00b pattern in the preamble (after the first
8-bits which are ignored), the entire frame will be ig-
nored. The MAC engine will wait for the network to go
inactive before attempting to receive additional frames.
Media Access Management
The basic requirement for all stations on the network is
to provide fairness of channel allocation. The
802.3/Ethernet protocols define a media access mecha-
nism which permits all stations to access the channel
with equality. Any node can attempt to contend for the
channel by waiting for a predetermined time (Inter Pack-
et Gap) after the last activity, before transmitting on the
media. The channel is a multidrop communications me-
dia (with various topological configurations permitted)
which allows a single station to transmit and all other
stations to receive. If two nodes simultaneously contend
for the channel, their signals will interact causing loss of
data, defined as a collision. It is the responsibility of the
MAC to attempt to avoid and recover from a collision, to
guarantee data integrity for the end-to-end transmission
to the receiving station.
Medium Allocation
The IEEE/ANSI 802.3 Standard (ISO/IEC 8802-3 1990)
requires that the CSMA/CD MAC monitor the medium
for traffic by watching for carrier activity. When carrier is
detected, the media is considered busy, and the MAC
should defer to the existing message.
The ISO 8802-3 (IEEE/ANSI 802.3) Standard also al-
lows optional two part deferral after a receive message.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:
Note: It s possible for the PLS carrier sense ndication to
fail to be asserted during a collision on the media. If the
deference process simply times the interFrame gap
based on this indication it is possible for a short
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AVC\\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVC\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:AMD 功能描述: |
| AM79C970AVC-G | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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