參數(shù)資料
型號(hào): AM79C970AKCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝: PLASTIC, QFP-132
文件頁(yè)數(shù): 141/219頁(yè)
文件大?。?/td> 1065K
代理商: AM79C970AKCW
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P R E L I M I N A R Y
AMD
141
Am79C970A
Table 30. BCR Registers
Programmability
RAP
MNEMONIC
Default
Name
User
EEPROM
0
MSRDA
0005h
Reserved
No
No
1
MSWRA
0005h
Reserved
No
No
2
MC
0002h
Miscellaneous Configuration
Yes
Yes
3
Reserved
N/A
Reserved
No
No
4
LNKST
00C0h
Link Status LED
Yes
Yes
5
LED1
0084h
LED1 Status
Yes
Yes
6
LED2
0088h
LED2 Status
Yes
Yes
7
LED3
0090h
LED3 Status
Yes
Yes
8
Reserved
N/A
Reserved
No
No
9
FDC
0000h
Full-Duplex Control
Yes
Yes
10–15
Reserved
N/A
Reserved
No
No
16
IOBASEL
N/A
Reserved
No
No
17
IOBASEU
N/A
Reserved
No
No
18
BSBC
9001h
Burst and Bus Control
Yes
Yes
19
EECAS
0002h
EEPROM Control and Status
Yes
No
20
SWS
0000h
Software Style
Yes
No
21
INTCON
N/A
Reserved
No
No
22
PCILAT
FF06h
PCI Latency
Yes
Yes
BCR0: Master Mode Read Active
Bit
Name
Description
31–16 RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 MSRDA
Reserved
H_RESET, the value in this
register will be 0005h. The set-
ting of this register has no effect
on any PCnet-PCI II controller
function. It is only included for
software compatibility with other
PCnet family devices.
locations.
After
Read always. MSRDA is read
only Write operations have
no effect.
BCR1: Master Mode Write Active
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 MSWRA
Reserved
H_RESET, the value in this reg-
ister will be 0005h. The setting of
this register has no effect on any
PCnet-PCI II controller function.
locations.
After
It is only included for software
compatibility with other PCnet
family devices.
Read always. MSWRA is read
only Write operations have
no effect.
BCR2: Miscellaneous Configuration
Bit
Name
Description
Note that bits 15–0 in this register
are programmable through the
external EEPROM. Reserved
bits and read-only bits should be
programmed to ZERO.
31–16 RES
Reserved locations. Written as
ZEROs and read as undefined.
15
RES
Reserved location. Written as
ZERO and read as undefined.
14
TMAULOOP
When set, this bit allows external
loopback packets to pass on to
the network through the T-MAU
interface, if the T-MAU interface
has been selected. If the T-MAU
interface has not been selected,
then this bit has no effect.
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