- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C970AKCW (ADVANCED MICRO DEVICES INC) PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C970AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 156/219頁 |
| 文件大?。?/td> | 1065K |
| 代理商： | AM79C970AKCW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁當(dāng)前第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁
AMD
P R E L I M I N A R Y
156
Am79C970A
Table 33. EEDET Setting
EEDET
Value
(BCR19[3])
EEPROM
Connected
Result of Automatic EEPROM Read
Operation Following H_RESET
Result if PREAD is Set to ONE
0
No
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID
is cleared to ZERO.
First TWO EESK clock cycles are
generated, then EEPROM read
operation is aborted and PVALID
is cleared to ZERO.
0
Yes
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
First TWO EESK clock cycles are
generated, then EEPROM read
operation is aborted and PVALID is
cleared to ZERO.
1
No
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID
is cleared to ZERO.
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID is
cleared to ZERO.
1
Yes
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
12–5
RES
Reserved locations. Written as
ZEROs, read as undefined.
4
EEN
EEPROM port enable. When this
bit is set to ONE, it causes the
values of ECS, ESK, and EDI to
be driven onto the EECS, EESK,
and EEDI pins, respectively. If
EEN is cleared to ZERO and no
EEPROM
read
currently active, then EECS will
be driven LOW and the EESK
and EEDI pins change their
function to
LED1
and
LNKST
and
are controlled by BCR5 and
BCR4, respectively.
function
is
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
EEN is cleared to ZERO by
H_RESET and is unaffected by
S_RESET or by setting the
STOP bit.
3
RES
Reserved location. Written as
ZERO and read as undefined.
2
ECS
EEPROM Chip Select. This bit is
used to control the value of the
EECS pin of the Microwire inter-
face when the EEN bit is set to
ONE and the PREAD bit is
cleared to ZERO. If EEN is set to
ONE and PREAD is cleared to
ZERO and ECS is set to ONE,
then the EECS pin will be forced
to a HIGH level at the rising edge
of the next clock following bit pro-
gramming. If EEN is set to ONE
and PREAD is cleared to ZERO
and ECS is cleared to ZERO,
then the EECS pin will be forced
to a LOW level at the rising edge
of the next clock following bit pro-
gramming. ECS has no effect on
the output value of the EECS pin
unless the PREAD bit is cleared
to ZERO and the EEN bit is set
to ONE.
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
ECS is cleared to ZERO by
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
1
ESK
EEPROM Serial Clock. This bit
and the EDI/EDO bit are used to
control host access to the
EEPROM. Values programmed
to this bit are placed on to the
EESK pin at the rising edge of the
next clock following bit program-
ming, except when the PREAD
bit is set to ONE or the EEN bit is
cleared to ZERO. If both the ESK
bit and the EDI/EDO bit values
are changed during one BCR19
write operation while EEN is set
to ONE, then setup and hold
times of the EEDI pin value with
respect to the EESK signal edge
are not guaranteed.
ESK has no effect on the EESK
pin unless the PREAD bit is
cleared to ZERO and the EEN bit
is set to ONE.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AVC\\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVC\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:AMD 功能描述: |
| AM79C970AVC-G | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。