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AMD
E-2
Am79C970A
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Pin to disable external transceiver or DC-to-DC
converter. Polarity of assertion state
programmable.
LIST OF REGISTER BIT CHANGES
PCI Configuration Space
Command Register
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ADSTEP (bit 7) now hardwired to ZERO. Was
hardwired to ONE.
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MEMEN (bit 1) now read/write accessible. Was
hardwired to ZERO.
Status Register
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PERR (bit 15) now cleared by H_RESET. Was not
effected by H_RESET.
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SERR (bit 14) now cleared by H_RESET. Was not
effected by H_RESET.
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RMABORT (bit 13) now cleared by H_RESET.
Was not effected by H_RESET.
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RTABORT (bit 12) now cleared by H_RESET. Was
not effected by H_RESET.
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STABORT (bit 11) now cleared by H_RESET. Was
not effected by H_RESET.
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DATAPERR (bit 8) now cleared by H_RESET.
Was not effected by H_RESET.
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FBTBC (bit 7) now hardwired to ONE. Was hard-
wired to ZERO.
Revision ID Register
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This 8-bit register is now hardwired to 1xh. It was
hardwired to 0xh.
Latency Timer Register
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This 8-bit register is now read/write accessible.
Was hardwired to ZERO.
I/O Base Address Register
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IOBASE (bits 31–5) now cleared by H_RESET.
Was not effected by H_RESET.
Memory Mapped I/O Base Address Register
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New 32-bit register. Was reserved, read as ZERO,
writes have no effect.
Expansion ROM Base Address Register
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New 32-bit register. Was reserved, read as ZERO,
writes have no effect.
Interrupt Line Register
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This 8-bit register is now cleared by H_RESET.
Was not effected by H_RESET.
MIN_GNT Register
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New 8-bit register. Was reserved, read as ZERO,
writes have no effect.
MAX_LAT Register
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New 8-bit register. Was reserved, read as ZERO,
writeshave no effect.
Control And Status Registers
CSR0: PCnet-PCI II controller Control and Status
Register
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In addition to the existing interrupt flags, INTR (bit
7), the interrupt summary bit, is also affected by
the new interrupt flags Excessive Deferral Interrupt
(EXDINT), Magic Packet Interrupt (MPINT) Sleep
Interrupt (SLPINT), System Interrupt (SINT) and
User Interrupt (UINT).
CSR3: Interrupt Masks and Deferral
Control
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New bit: DXSUFLO (bit 6), Disable Transmit Stop
on Underflow error. Was reserved location, read
and written as ZERO.
CSR4: Test and Features Control
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New bit: UINTCMD (bit 7), User Interrupt Com-
mand. Was reserved location, read and written
as ZERO.
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New bit: UINT (bit 6), User Interrupt. Was reserved
location, read as ZERO, written as ONE or ZERO.
CSR5:
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New bit: TOKINTD (bit 15), Transmit OK Interrupt
Disable. Was reserved location, read and written
as ZERO.
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New bit: LTINTEN (bit 14), Last Transmit Interrupt
Enable. Was reserved location, read and written as
ZERO.
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New bit: SINT (bit 11), System Interrupt. Was re-
served location, read and written as ZERO.
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New bit: SINTE (bit 10), System Interrupt Enable.
Was reserved location, read and written as ZERO.
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New bit: SLPINT (bit 9), Sleep Interrupt. Was re-
served location, read and written as ZERO.
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New bit: SLPINTE (bit 8), Sleep Interrupt Enable.
Was reserved location, read and written as ZERO.
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New bit: EXDINT (bit 7), Excessive Deferral Inter-
rupt. Was reserved location, read and written as
ZERO.
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New bit: EXDINTE (bit 6), Excessive Deferral Inter-
rupt Enable. Was reserved location, read and writ-
ten as ZERO.
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New bit: MPPLBA (bit 5), Magic Packet Physical
Logical Broadcast Accept. Was reserved location,
read and written as ZERO.
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New bit: MPINT (bit 4), Magic Packet Interrupt.
Was reserved location, read and written as ZERO.
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New bit: MPINTE (bit 3), Magic Packet Interrupt
Enable. Was reserved location, read and written as
ZERO.
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New bit: MPEN (bit 2), Magic Packet Enable. Was
reserved location, read and written as ZERO.