
AMD
P R E L I M I N A R Y
128
Am79C970A
S_RESET or by setting the
STOP bit.
CSR26: Next Receive Descriptor Address Lower
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of
the next receive descriptor
address pointer.
Read/Write
accessible
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
15–0
NRDAL
only
CSR27: Next Receive Descriptor Address Upper
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of
the next receive descriptor
address pointer.
Read/Write
accessible
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
15–0 NRDAU
only
CSR28: Current Receive Descriptor Address
Lower
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of
the current receive descriptor
address pointer.
Read/Write
accessible
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
15–0
CRDAL
only
CSR29: Current Receive Descriptor Address
Upper
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 CRDAU
Contains the upper 16 bits of
the current receive descriptor
address pointer.
Read/Write
accessible
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
only
CSR30: Base Address of Transmit
Descriptor Ring Lower
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
base address of the transmit
descriptor ring.
Read/Write
accessible
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
15–0
BADXL
only
CSR31: Base Address of Transmit
Descriptor Ring Upper
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
base address of the transmit
descriptor ring.
Read/Write
accessible
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
15–0 BADXU
only
CSR32: Next Transmit Descriptor Address Lower
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of
the next transmit descriptor
address pointer.
Read/Write
accessible
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
15–0
NXDAL
only