參數(shù)資料
型號(hào)： AM79C970AKC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP13
封裝： CARRIER RING, PLASTIC, QFP-132
文件頁(yè)數(shù)： 157/219頁(yè)
文件大?。?/td> 1065K
代理商： AM79C970AKC
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P R E L I M I N A R Y
AMD
157
Am79C970A
Table 34. Microwire Interface Pin Assignment
PREAD or
Auto Read in
Progress
RST
Pin
EEN
EECS
EESK
EEDI
High
X
X
Low
Tri-State
Tri-State
Low
1
X
Active
Active
Active
Low
0
1
BCR19[2]
BCR19[1]
BCR19[0]
Low
0
0
Low
LED1
LNKST
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
ESK is set to ONE by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
0
EDI/EDO
EEPROM
Data Out. Data that is written to
this bit will appear on the EEDI
output of the Microwire interface,
except when the PREAD bit is set
to ONE or the EEN bit is cleared
to ZERO. Data that is read from
this bit reflects the value of
the
EEDO
input
Microwire interface.
Data
In/EEPROM
of
the
EDI/EDO has no effect on the
EEDI pin unless the PREAD bit is
cleared to ZERO and the EEN bit
is set to ONE.
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
EDI/EDO is cleared to ZERO by
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
BCR20: Software Style
Bit
Name
Description
This register is an alias of the lo-
cation CSR58. Accesses to/from
this register are equivalent to ac-
cesses to CSR58.
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–11
RES
Reserved locations. Written as
ZEROs and read as undefined.
10
APERREN
Advanced Parity Error Handling
Enable. When APERREN is set
to ONE, the BPE bits (RMD1 and
TMD1, bit 23) are used to indi-
cated parity error in data
transfers to the receive and
transmit buffers. Note that since
the
advanced
parity
error
handling uses an additional bit in
the descriptor, SWSTYLE (bits
7–0 of this register) must be set
to ONE, TWO or THREE to pro-
gram the PCnet-PCI II controller
to use 32-bitsoftware structures.
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur
when the PCnet-PCI II controller
is the target of the transfer.
Read accessible always, write
accessible only when either the
STOP or the SPND bit is set.
APERREN
is
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
cleared
by
9
CSRPCNET
CSR PCnet-ISA configuration.
When set, this bit indicates that
the PCnet-PCI II controller regis-
ter bits of CSR4 and CSR3 will
map directly to the CSR4 and
CSR3 bits of the PCnet-ISA
(Am79C960)
device.
cleared, this bit indicates that
PCnet-PCI II controller register
bits of CSR4 and CSR3 will map
directly to the CSR4 and
CSR3
bits
of
(Am79C900) device.
When
the
ILACC
The value of CSRPCNET is
determined by the PCnet-PCI II
controller
according
setting of the Software Style
(SWSTYLE,
bits
this register).
to
the
7–0
of
Read
CSRPCNET is read only. Write
operations will be ignored.
CSRPCNET will be set after
H_RESET (since SWSTYLE de-
faults to ZERO) and is not
affected by S_RESET or by set-
ting the STOP bit.
accessible
always.
8
SSIZE32
32-Bit Software Size. When set,
this bit indicates that the
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970AKC\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:
AM79C970AKC\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
AM79C970AKCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVC 制造商:Advanced Micro Devices 功能描述:
AM79C970AVC\\W 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:
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