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參數(shù)資料
| 型號： | AM79C960KC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120 |
| 封裝： | CARRIER RING, PLASTIC, QFP-120 |
| 文件頁數(shù)： | 50/127頁 |
| 文件大?。?/td> | 814K |
| 代理商： | AM79C960KC |
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P R E L I M I N A R Y
AMD
1-392
Am79C960
Refresh Cycles
Although the PCnet-ISA controller is neither an origina-
tor or a receiver of refresh cycles, it does need to avoid
unintentional activity during a refresh cycle in bus mas-
ter mode. A refresh cycle is performed as follows: First,
the
REF
signal goes active. Then a valid refresh ad-
dress is placed on the address bus.
MEMR
goes active,
the refresh is performed, and
MEMR
goes inactive. The
refresh address is held for a short time and then goes
invalid. Finally,
REF
goes inactive. During a refresh cy-
cle, as indicated by
REF
being active, the PCnet-ISA
controller inhibits its
SMEMR
inputs and ignores
DACK
if it goes active until it goes inactive. It is necessary to
ignore
DACK
during a refresh because some mother-
boards generate a false
DACK
at that time.
Address PROM Cycles
The Address PROM is a small (16 bytes) 8-bit PROM
connected to the PCnet-ISA controller Private Data Bus.
The PCnet-ISA controller will support only 8-bit ISA I/O
bus cycles for the address PROM; this limitation is trans-
parent to software and does not preclude 16-bit
software I/O accesses. An access cycle begins with the
Permanent Master driving AEN LOW, driving the ad-
dresses valid, and driving
IOR
active. The PCnet-ISA
controller detects this combination of signals and arbi-
trates for the Private Data Bus (PRDB) if necessary.
IOCHRDY is driven LOW during accesses to the ad-
dress PROM.
When the Private Data Bus becomes available, the
PCnet-ISA controller drives
APCS
active, releases
IOCHRDY, turns on the data path from PRD0-7, and en-
ables the SD0-7 drivers (but not SD8-15). During this
bus cycle,
IOCS16
is not driven active. This condition is
maintained until
IOR
goes inactive, at which time the
bus cycle ends. Data is removed from SD0-7 within
30 ns.
Ethernet Controller Register Cycles
Ethernet controller registers (RAP, RDP, IDP) are natu-
rally 16-bit resources but can be configured to operate
with 8-bit bus cycles provided the proper protocol is fol-
lowed. If
IOCS16
has never gone HIGH since RESET,
then all controller register bus cycles will be 8-bit only.
This situation would occur if the
IOCS16
pin is left un-
connected to the ISA bus and tied to ground. This
means on a read, the PCnet-ISA controller will only drive
the low byte of the system data bus; if an odd byte is
accessed, it will be swapped down. The high byte of the
system data bus is never driven by the PCnet-ISA con-
troller under these conditions. On a write cycle, the even
byte is placed in a holding register. An odd byte write is
internally swapped up and augmented with the even
byte in the holding register to provide an internal 16-bit
write. This allows the use of 8-bit I/O bus cycles which
are more likely to be compatible with all ISA-compatible
clones, but requires that both bytes be written in immedi-
ate succession. This is accomplished simply by treating
the PCnet-ISA controller controller registers as 16-bit
software resources. The motherboard will convert the
16-bit accesses done by software into two sequential
8-bit accesses, an even byte access followed immedi-
ately by an odd byte access.
An access cycle begins with the Permanent Master driv-
ing AEN LOW, driving the address valid, and driving
IOR
or
IOW
active. The PCnet-ISA controller detects this
combination of signals and drives IOCHRDY LOW.
IOCS16
will also be driven LOW if 16-bit I/O bus cycles
are enabled. When the register data is ready, IOCHRDY
will be released HIGH. This condition is maintained until
IOR
or
IOW
goes inactive, at which time the bus cycle
ends.
RESET Cycles
A read to the reset address causes an PCnet-ISA con-
troller reset. This has the same effect as asserting the
RESET pin on the PCnet-ISA controller, such as hap-
pens during a system power-up or hard boot. The
subsequent write cycle needed in the NE2100 LANCE
based family of Ethernet cards is not required but does
not have any harmful effects.
IOCS16
is not asserted in
this cycle.
ISA Configuration Register Cycles
The ISA configuration registers are accessed by placing
the address of the desired register into the RAP and
reading the IDP. The ISACSR bus cycles are identical
to all other PCnet-ISA controller register bus cycles.
Boot PROM Cycles
The Boot PROM is an 8-bit PROM connected to the
PCnet-ISA controller Private Data Bus (PRDB) and can
occupy up to 16 Kbytes of address space. Since the
PCnet-ISA controller does not generate
MEMCS16
,
only 8-bit ISA memory bus cycles to the boot PROM are
supported in Bus Master Mode; this limitation is trans-
parent to software and does not preclude 16-bit
software memory accesses. A boot PROM access cycle
begins with the Permanent Master driving the ad-
dresses valid,
REF
inactive, and
SMEMR
active. (AEN
is not involved in memory cycles). The PCnet-ISA con-
troller detects this combination of signals, drives
IOCHRDY LOW, and reads a byte out of the Boot
PROM. The data byte read is driven onto the lower sys-
tem data bus lines and IOCHRDY is released. This
condition is maintained until
SMEMR
goes inactive, at
which time the access cycle ends.
The
BPCS
signal generated by the PCnet-ISA controller
is three 20 MHz clock cycles wide (150 ns). Including
delays, the Boot PROM has 120 ns to respond to the
BPCS
signal from the PCnet-ISA controller. This signal
is intended to be connected to the
CS
pin on the boot
PROM, with the PROM
OE
pin tied to ground. When us-
ing a PROM with an access time slower than 120 ns,
BPCS
may be connected to the
OE
pin of the boot
PROM while tying the PROM
CS
pin to ground.
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|---|---|
| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
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| AM79C961AKC | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961A | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AKIW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
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| AM79C960KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C960KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C961 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961/AM79C961A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF) |
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