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參數(shù)資料
| 型號(hào)： | AM79C960KC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120 |
| 封裝： | CARRIER RING, PLASTIC, QFP-120 |
| 文件頁(yè)數(shù)： | 39/127頁(yè) |
| 文件大?。?/td> | 814K |
| 代理商： | AM79C960KC |
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P R E L I M I N A R Y
AMD
1-381
Am79C960
mended when InterFrameSpacingPart1 is
other than zero:
(1) Upon completing a transmission, start timing
the interpacket gap, as soon as transmitting
and carrierSense are both false.
(2) When timing an interpacket gap following re-
ception, reset the interpacket gap timing if
carrier Sense becomes true during the first 2/3
of the nterpacket gap timing nterval. During the
final 1/3 of the interval the timer shall not be re-
set to ensure fair access to the medium. An
initial period shorter than 2/3 of the interval is
permissible including zero.”
The MAC engine implements the optional receive two
part deferral algorithm, with a first part inter-frame-spac-
ing time of 6.0
μ
s. The second part of the
inter-frame-spacing interval is therefore 3.6
μ
s.
The PCnet-ISA controller will perform the two-part
deferral algorithm as specified in Section 4.2.8 (Process
Deference). The Inter Packet Gap (IPG) timer will start
timing the 9.6
μ
s InterFrameSpacing after the receive
carrier is de-asserted. During the first part deferral
(InterFrameSpacingPart1 - IFS1) the PCnet-ISA con-
troller will defer any pending transmit frame and respond
to the receive message. The IPG counter will be reset to
zero continuously until the carrier de-asserts, at which
point the IPG counter will resume the 9.6
μ
s count once
again. Once the IFS1 period of 6.0
μ
s has elapsed, the
PCnet-ISA controller will begin timing the second part
deferral (InterFrameSpacingPart2 - IFS2) of 3.6
μ
s.
Once IFS1 has completed, and IFS2 has commenced,
the PCnet-ISA controller will not defer to a receive pack-
et if a transmit packet is pending. This means that the
PCnet-ISA controller will not attempt to receive the re-
ceive packet, since it will start to transmit, and generate
a collision at 9.6
μ
s. The PCnet-ISA controller will guar-
antee to complete the preamble (64-bit) and jam (32-bit)
sequence before ceasing transmission and invoking the
random backoff algorithm.
In addition, transmit two part deferral is implemented as
an option which can be disabled using the DXMT2PD bit
(CSR3). Two-part deferral after transmission is useful
for ensuring that severe IPG shrinkage cannot occur in
specific circumstances, causing a transmit message to
follow a receive message so closely as to make them
indistinguishable.
During the time period immediately after a transmission
has been completed, the external transceiver (in the
case of a standard AUI connected device), should gen-
erate the SQE Test message (a nominal 10 MHz burst of
5-15 Bit Times duration) on the CI
±
pair (within 0.6
μ
s –
1.6
μ
s after the transmission ceases). During the time
period in which the SQE Test message is expected the
PCnet-ISA controller will not respond to receive carrier
sense.
See ANSI/IEEE Std 802.3-1990 Edition,
7.2.4.6 (1)):
“At the conclusion of the output function, the
DTE opens a time window during which it ex-
pects to see the signal_quality_error signal
asserted on the Control In circuit. The time win-
dow begins when the CARRIER_STATUS
becomes CARRIER_OFF. If execution of the
output function does not cause CARRIER_ON
to occur, no SQE test occurs in the DTE. The
duration of the window shall be at least 4.0
μ
s
but no more than 8.0
μ
s. During the time win-
dow the Carrier Sense Function is inhibited.”
The PCnet-ISA controller implements a carrier sense
“blinding” period within 0 – 4.0
μ
s from deassertion of
carrier sense after transmission. This effectively means
that when transmit two part deferral is enabled
(DXMT2PD is cleared) the IFS1 time is from 4
μ
s to 6
μ
s
after a transmission. However, since IPG shrinkage be-
low 4
μ
s will rarely be encountered on a correctly
configured network, and since the fragment size will be
larger than the 4
μ
s blinding window, then the IPG
counter will be reset by a worst case IPG shrinkage/frag-
ment scenario and the PCnet-ISA controller will defer its
transmission. In addition, the PCnet-ISA controller will
not restart the “blinding” period if carrier is detected
within the 4.0
μ
s – 6.0
μ
s IFS1 period, but will com-
mence timing of the entire IFS1 period.
Contention Resolution (Collision Handling)
Collision detection is performed and reported to the
MAC engine by the integrated Manchester Encoder/
Decoder (MENDEC).
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC Engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the pream-
ble/SFD has been completed, but prior to 512 bits being
transmitted, the MAC Engine will abort the transmis-
sion, and append the jam sequence immediately. The
jam sequence is a 32-bit all zeroes pattern.
The MAC Engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to normal
collisions (those within the slot time). Detection of colli-
sion will cause the transmission to be re-scheduled,
dependent on the backoff time that the MAC Engine
computes. If a single retry was required, the ONE bit will
be set in the Transmit Frame Status (TMD1 in the Trans-
mit Descriptor Ring). If more than one retry was
required, the MORE bit will be set. If all 16 attempts ex-
perienced collisions, the RTRY bit (in TMD2) will be set
(ONE and MORE will be clear), and the transmit mes-
sage will be flushed from the FIFO. If retries have been
disabled by setting the DRTY bit in the MODE register
(CSR15), the MAC Engine will abandon transmission of
the frame on detection of the first collision. In this case,
only the RTRY bit will be set and the transmit message
will be flushed from the FIFO.
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
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| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
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| AM79C960KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C960KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller |
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| AM79C961/AM79C961A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF) |
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