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參數(shù)資料
| 型號(hào)： | AM79C960KC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120 |
| 封裝： | CARRIER RING, PLASTIC, QFP-120 |
| 文件頁(yè)數(shù)： | 38/127頁(yè) |
| 文件大?。?/td> | 814K |
| 代理商： | AM79C960KC |
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P R E L I M I N A R Y
AMD
1-380
Am79C960
network is protected from gross errors due to inability of
the host to keep pace with the MAC engine activity.
On completion of transmission, the following transmit
status is available in the appropriate TMD and CSR
areas:
I
The exact number of transmission retry attempts
(ONE, MORE, or RTRY)
I
Whether the MAC engine had to Defer (DEF)
due to channel activity
I
Loss of Carrier, indicating that there was an
interruption in the ability of the MAC engine to
monitor its own transmission. Repeated LCAR
errors indicate a potentially faulty transceiver
or network connection.
I
Late Collision (LCOL) indicates that the
transmission suffered a collision after the slot time.
This is indicative of a badly configured network.
Late collisions should not occur in a normal
operating network.
I
Collision Error (CERR) indicates that the
transceiver did not respond with an SQE Test
message within the predetermined time after a
transmission completed. This may be due to a
failed transceiver, disconnected or faulty trans-
ceiver drop cable, or the fact the transceiver does
not support this feature (or the feature is disabled).
In addition to the reporting of network errors, the MAC
engine will also attempt to prevent the creation of any
network error due to the inability of the host to service
the MAC engine. During transmission, if the host fails to
keep the Transmit FIFO filled sufficiently, causing an un-
derflow, the MAC engine will guarantee the message is
either sent as a runt packet (which will be deleted by the
receiving station) or has an invalid FCS (which will also
cause the receiver to reject the message).
The status of each receive message is available in the
appropriate RMD and CSR areas. FCS and Framing er-
rors (FRAM) are reported, although the received frame
is still passed to the host. The FRAM error will only be
reported if an FCS error is detected and there are a non-
integral number of bits in the message. The MAC engine
will ignore up to seven additional bits at the end of a
message (dribbling bits), which can occur under normal
network operating conditions. The reception of eight ad-
ditional bits will cause the MAC engine to de-serialize
the entire byte, and will result in the received message
and FCS being modified.
The PCnet-ISA controller can handle up to 7 dribbling
bits when a received packet terminates. During the re-
ception, the CRC is generated on every serial bit
(including the dribbling bits) coming from the cable, al-
though the internally saved CRC value is only updated
on the eighth bit (on each byte boundary). The framing
error is reported to the user as follows:
1.
If the number of the dribbling bits are 1 to 7 and there
is no CRC error, then there is no Framing error
(FRAM = 0).
2.
If the number of the dribbling bits are less than 8 and
there is a CRC error, then there is also a Framing
error (FRAM = 1).
3.
If the number of dribbling bits = 0, then there is no
Framing error. There may or may not be a CRC
(FCS) error.
Counters are provided to report the Receive Collision
Count and Runt Packet Count and used for network sta-
tistics and utilization calculations.
Note that if the MAC engine detects a received packet
which has a 00b pattern in the preamble (after the first
8 bits, which are ignored), the entire packet will be ig-
nored. The MAC engine will wait for the network to go
inactive before attempting to receive the next packet.
Media Access Management
The basic requirement for all stations on the network is
to provide fairness of channel allocation. The
802.3/Ethernet protocol defines a media access mecha-
nism which permits all stations to access the channel
with equality. Any node can attempt to contend for the
channel by waiting for a predetermined time (Inter
Packet Gap interval) after the last activity, before trans-
mitting on the medium. The channel is a multidrop
communications medium (with various topological con-
figurations permitted) which allows a single station to
transmit and all other stations to receive. If two nodes
simultaneously contend for the channel, their signals
will interact, causing loss of data (defined as a collision).
It is the responsibility of the MAC to attempt to avoid and
recover from a collision, to guarantee data integrity for
the end-to-end transmission to the receiving station.
Medium Allocation (Collision Avoidance)
The IEEE 802.3 Standard (ISO/IEC 8802-3 1990) re-
quires that the CSMA/CD MAC monitor the medium
traffic by looking for carrier activity. When carrier is de-
tected the medium is considered busy, and the MAC
should defer to the existing message.
The IEEE 802.3 Standard also allows optional two part
deferral after a receive message.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:
“Note
: It is possible for the PLS carrier sense
indication to fail to be asserted during a collision
on the media. If the deference process simply
times the interpacket gap based on this indica-
tion it is possible for a short interFrame gap to
be generated, leading to a potential reception
failure of a subsequent frame. To enhance sys-
tem
robustness
the
measures, as specified in 4.2.8, are recom-
following
optional
相關(guān)PDF資料 |
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| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C961AKCW | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AKC | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961A | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AKIW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C960KC/W | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:LAN Node Controller |
| AM79C960KCW | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C961 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961/AM79C961A | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF) |
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