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| 型號： | AM45DL32X8G |
| 英文描述： | 200NS, FLATPACK, 883C; LEV B COMPLIANT(EEPROM) |
| 中文描述： | Am45DL32x8G -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 58/64頁 |
| 文件大?。?/td> | 1191K |
| 代理商： | AM45DL32X8G |
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August 28, 2002
Am45DL32x8G
57
P R E L I M I N A R Y
CompactCell SRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. t
CW
is measured from CE1#s going low to the end of write.
3. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
4. t
AS
is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
Figure 30.
CompactCell SRAM Write Cycle
—
WE# Control
Parameter
Symbol
Description
Speed
Unit
70
85
t
WC
Write Cycle Time
Min
70
85
ns
t
Cw
Chip Enable to End of Write
Min
60
70
ns
t
AS
Address Setup Time
Min
0
ns
t
AW
Address Valid to End of Write
Min
60
70
ns
t
BW
UB#s, LB#s to End of Write
Min
60
70
ns
t
WP
Write Pulse Time
Min
50
60
ns
t
WR
Write Recovery Time
Min
0
ns
t
WHZ
Write to Output High-Z
Min
0
ns
Max
20
25
t
DW
Data to Write Time Overlap
Min
40
45
ns
t
DH
Data Hold from Write Time
Min
0
ns
t
OW
End Write to Output Low-Z
min
5
ns
Address
CE1#s
Data Undefined
WE#
Data In
Data Out
t
WC
t
CW
(See Note 1)
t
AW
High-Z
High-Z
Data Valid
CE2s
t
CW
(See Note 1)
t
WP
(See Note 4)
t
(See Note 3)
t
WR
t
DW
t
DH
t
OW
t
WHZ
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