參數(shù)資料
型號： AM45DL32X8G
英文描述： 200NS, FLATPACK, 883C; LEV B COMPLIANT(EEPROM)
中文描述： Am45DL32x8G -堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁數(shù)： 4/64頁
文件大小： 1191K
代理商： AM45DL32X8G
August 28, 2002
Am45DL32x8G
3
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash memory Block Diagram . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions ....................................7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . . .9
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
IH
; CC
SRAMByte Mode, CIOs = V
......................................................11
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SS
; CC
SRAMWord Mode, CIOs = V
CC
.....................................................12
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
IL
; CC
SRAMByte Mode, CIOs = V
......................................................13
Flash Device Bus Operations . . . . . . . . . . . . . . .13
Requirements for Reading Array Data ...................................13
Writing Commands/Command Sequences ............................14
Accelerated ProgramOperation ..........................................14
Autoselect Functions ...........................................................14
Simultaneous Read/Write Operations with Zero Latency .......14
Automatic Sleep Mode ...........................................................15
RESET# Hardware Reset Pin ...............................................15
Output Disable Mode ..............................................................15
Table 5. Device Bank Division ........................................................15
Table 6. Top Boot Sector Addresses .............................................16
Table 8. BottomBoot Sector Addresses .........................................18
Table 10. Top Boot Sector/Sector Block Addresses
forProtection/Unprotection .............................................................20
Table 11. BottomBoot Sector/Sector Block Addresses
forProtection/Unprotection .............................................................20
Write Protect (WP#) ................................................................21
Temporary Sector Unprotect ..................................................21
Figure 1. Temporary Sector Unprotect Operation........................... 21
Figure 2. In-SystemSector Protect/Unprotect Algorithms.............. 22
SecSi
(Secured Silicon) Sector
FlashMemoryRegion ............................................................23
Hardware Data Protection ......................................................23
Low V
CC
Write Inhibit ...........................................................24
Write Pulse
“
Glitch
”
Protection ............................................24
Logical Inhibit ......................................................................24
Power-Up Write Inhibit .........................................................24
Common Flash Memory Interface (CFI) . . . . . . .24
Flash Command Definitions . . . . . . . . . . . . . . . . 27
Reading Array Data ................................................................27
Reset Command .....................................................................27
Autoselect Command Sequence ............................................27
Enter SecSi
Sector/Exit SecSi Sector
Command Sequence ..............................................................27
Byte/Word ProgramCommand Sequence .............................28
Unlock Bypass Command Sequence ..................................28
Figure 3. ProgramOperation.......................................................... 29
Chip Erase Command Sequence ...........................................29
Sector Erase Command Sequence ........................................29
Erase Suspend/Erase Resume Commands ...........................30
Figure 4. Erase Operation............................................................... 30
Table 17. Autoselect Device IDs (Word Mode) ...............................31
Table 19. Autoselect Device IDs (Byte Mode) ................................32
Flash Write Operation Status . . . . . . . . . . . . . . . . 33
DQ7: Data#Polling .................................................................33
Figure 5. Data# Polling Algorithm.................................................. 33
DQ6: Toggle Bit I ....................................................................34
Figure 6. Toggle Bit Algorithm....................................................... 34
DQ2: Toggle Bit II ...................................................................35
Reading Toggle Bits DQ6/DQ2 ...............................................35
DQ5: Exceeded Timng Limts ................................................35
DQ3: Sector Erase Timer .......................................................35
Table 20. Write Operation Status ...................................................36
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 37
Figure 7. MaximumNegative OvershootWaveform...................... 37
Figure 8. MaximumPositive OvershootWaveform........................ 37
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 38
CMOS Compatible ..................................................................38
Figure 9. I
CC1
Current vs. Time (Showing Active and
AutomaticSleepCurrents)............................................................. 39
Figure 10. Typical I
vs. Frequency............................................ 39
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Test Setup.................................................................... 41
Figure 12. Input Waveforms and Measurement Levels................. 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
CompactCell SRAMCE#s Timng ..........................................42
Figure 13. Timng Diagramfor Alternating
Between CompactCell SRAM and Flash....................................... 42
Read-Only Operations ...........................................................43
Figure 14. Read Operation Timngs............................................... 43
Hardware Reset (RESET#) ....................................................44
Figure 15. Reset Timngs............................................................... 44
Word/Byte Configuration (CIOf) ..............................................45
Figure 16. CIOf Timngs for Read Operations................................ 45
Figure 17. CIOf Timngs for Write Operations................................ 45
Flash Erase and ProgramOperations ....................................46
Figure 18. ProgramOperation Timngs.......................................... 47
Figure 19. Accelerated ProgramTimng Diagram.......................... 47
Figure 20. Chip/Sector Erase Operation Timngs.......................... 48
Figure 21. Back-to-back Read/Write Cycle Timngs...................... 49
Figure 22. Data#Polling Timngs (During Embedded Algorithms). 49
Figure 23. Toggle Bit Timngs (During Embedded Algorithms)...... 50
Figure 24. DQ2 vs. DQ6................................................................. 50
Temporary Sector Unprotect ..................................................51
Figure 25. Temporary Sector Unprotect Timng Diagram.............. 51
Figure 26. Sector/Sector Block Protect and
Unprotect Timng Diagram............................................................. 52
Alternate CE#f Controlled Erase and ProgramOperations ....53
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program
OperationTimngs.......................................................................... 54
Power Up Time .......................................................................55
Read Cycle .............................................................................55
Figure 28. CompactCell SRAMRead Cycle
—
Address Controlled 55
Read Cycle .............................................................................56
Figure 29. CompactCell SRAMRead Cycle.................................. 56
Write Cycle .............................................................................57
Figure 30. CompactCell SRAMWrite Cycle
—
WE# Control........... 57
Figure 31. CompactCell SRAMWrite Cycle
—
CE1#s Control........ 58
Figure 32. CompactCell SRAMWrite Cycle
—
UB#s and LB#s Control.................................................................. 59
Flash Erase And Programming Performance . . 60
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 60
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 60
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 60
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