- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362277 > AM45DL32X8G 200NS, FLATPACK, 883C; LEV B COMPLIANT(EEPROM) PDF資料下載
參數(shù)資料
| 型號： | AM45DL32X8G |
| 英文描述： | 200NS, FLATPACK, 883C; LEV B COMPLIANT(EEPROM) |
| 中文描述： | Am45DL32x8G -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 30/64頁 |
| 文件大小： | 1191K |
| 代理商： | AM45DL32X8G |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
August 28, 2002
Am45DL32x8G
29
P R E L I M I N A R Y
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables
16
and
18
show the address and data requirements for the
chip erase command sequence.
When the Embedded Erase algorithm is complete,
that bank returns to the read mode and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. Refer to the Flash Write Operation Status
section for information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a
hardware reset
im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 4
illustrates the algorithm for the erase opera-
tion. Refer to the Flash Erase and Program Opera-
tions tables in the AC Characteristics section for
parameters, and
Figure 20
section for timing dia-
grams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Tables
16
and
18
show
the address and data requirements for the sector
erase command sequence.
The device does
not
require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 80 μs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 80
μs, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written.
Any command other than
Sector Erase or Erase Suspend during the
time-out period resets that bank to the read mode.
The system must rewrite the command sequence and
any additional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing bank. The system can de-
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note:
See Tables
16
and
18
for program command
sequence.
相關PDF資料 |
PDF描述 |
|---|---|
| AM45DL6408G | 250NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM) |
| AM46-0006 | 250NS, LCC, 883C; LEV B FULLY COMPLIANT(EEPROM) |
| AM46-0007 | DIE(EEPROM) |
| AM486DE2 | Am486DE2 Microprocessor Data Sheet |
| AM486DX | Am486DX - Am486DX Block Diagram |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM45DL6408G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) (Preliminary) |
| AM45N06-16D | 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:N-Channel 60-V (D-S) MOSFET |
| AM45W | 制造商:ECLIPSE 功能描述:BLADE LOW ALLOY 12X1/2X0.025X18TPI |
| AM460 | 制造商:AME 制造商全稱:Analog Microelectronics 功能描述:Industrial Converter and Protector IC |
| AM46-0006 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
發(fā)布緊急采購，3分鐘左右您將得到回復。