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參數(shù)資料
| 型號(hào)： | ADV7183BKSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER NTSC 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Interfacing AV Converters to Blackfin Processors |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | 投影儀，錄音機(jī)，安全 |
| 電壓 - 電源，模擬： | 3.15 V ~ 3.45 V |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 2 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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ADV7183B
Rev. B | Page 16 of 100
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVE MODES
Power-Down
PDBP, Address 0x0F[2]
The digital core of the ADV7183B can be shut down by using
the PWRDN pin and the PWRDN bit (see below). The PDBP
controls which of the two pins has the higher priority. The
default is to give priority to the PWRDN pin. This allows the
user to have the ADV7183B powered down by default.
When PDBD is 0 (default), the digital core power is controlled
by the PWRDN pin (the bit is disregarded).
When PDBD is 1, the bit has priority (the pin is disregarded).
PWRDN, Address 0x0F[5]
Setting the PWRDN bit switches the ADV7183B into a chip-
wide power-down mode. The power-down stops the clock from
entering the digital section of the chip, thereby freezing its
operation. No I2C bits are lost during power-down. The
PWRDN bit also affects the analog blocks and switches them
into low current modes. The I2C interface is unaffected and
remains operational in power-down mode.
The ADV7183B leaves the power-down state if the PWRDN
bit is set to 0 (via I2C), or if the overall part is reset using the
RESET pin.
PDBP must be set to 1 for the PWRDN bit to power down the
ADV7183B.
When PWRDN is 0 (default), the chip is operational.
When PWRDN is 1, the ADV7183B is in chip-wide power-down.
ADC Power-Down Control
The ADV7183B contains three 10-bit ADCs (ADC 0, ADC 1,
and ADC 2). If required, each ADC can be powered down
individually.
The ADCs should be powered down when in:
CVBS mode. ADC 1 and ADC 2 should be powered down
to save on power consumption.
S-Video mode. ADC 2 should be powered down to save on
power consumption.
PWRDN_ADC_0, Address 0x3A[3]
When PWRDN_ADC_0 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_0 is 1, ADC 0 is powered down.
PWRDN_ADC_1, Address 0x3A[2]
When PWRDN_ADC_1 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_1 is 1, ADC 1 is powered down.
PWRDN_ADC_2, Address 0x3A[1]
When PWRDN_ADC_2 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_2 is 1, ADC 2 is powered down.
RESET CONTROL
Chip Reset (RES), Address 0x0F[7]
Setting this bit, equivalent to controlling the RESET pin on the
ADV7183B, issues a full chip reset. All I2C registers are reset to
their default values. (Some register bits do not have a reset value
specified. They keep their last written value. Those bits are
marked as having a reset value of x in the register table.) After
the reset sequence, the part immediately starts to acquire the
incoming video signal.
After setting the RES bit (or initiating a reset via the pin), the
part returns to the default mode of operation with respect to its
primary mode of operation. All I2C bits are loaded with their
default values, making this bit self-clearing.
Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I2C writes are
performed.
The I2C master controller receives a no acknowledge condition
on the ninth clock cycle when chip reset is implemented. See
the
148H
MPU Port Description section.
When RES is 0 (default), operation is normal.
When RES is 1, the reset sequence starts.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7183KST | 制造商:Analog Devices 功能描述:Video Decoder 2ADC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:VIDEO DECODER I.C. - Bulk |
| ADV7184 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
| ADV7184BSTZ | 功能描述:IC DECODER VID SDTV MULTI 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7185 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
| ADV7185KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
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