- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10972 > ADV7183BKSTZ (Analog Devices Inc)IC VIDEO DECODER NTSC 80-LQFP PDF資料下載
參數(shù)資料
| 型號： | ADV7183BKSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER NTSC 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Interfacing AV Converters to Blackfin Processors |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | 投影儀，錄音機(jī)，安全 |
| 電壓 - 電源，模擬： | 3.15 V ~ 3.45 V |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 2 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁
ADV7183B
Rev. B | Page 40 of 100
VS and FIELD Configuration
The following controls allow the user to configure the behavior
of the VS and FIELD output pins and to generate embedded AV
codes:
ADV encoder-compatible signals via NEWAVMODE
PVS, PF
HVSTIM
VSBHO, VSBHE
VSEHO, VSEHE
For NTSC control:
NVBEGDELO, NVBEGDELE, NVBEGSIGN,
NVBEG[4:0]
NVENDDELO, NVENDDELE, NVENDSIGN,
NVEND[4:0]
NFTOGDELO, NFTOGDELE, NFTOGSIGN,
NFTOG[4:0]
For PAL control:
PVBEGDELO, PVBEGDELE, PVBEGSIGN,
PVBEG[4:0]
PVENDDELO, PVENDDELE, PVENDSIGN,
PVEND[4:0]
PFTOGDELO, PFTOGDELE, PFTOGSIGN,
PFTOG[4:0]
NEWAVMODE New AV Mode, Address 0x31[4]
When NEWAVMODE is 0, EAV/SAV codes are generated to
suit ADI encoders. No adjustments are possible.
Setting NEWAVMODE to 1 (default) enables the manual posi-tion
of the Vsync, Field, and AV codes using Register 0x34 to Register
0x37 and Register 0xE5 to Register 0xEA. Default register settings
are CCIR656-compliant; see
211H
Figure 21 for NTSC and
212H
Figure 26 for
PAL. For recommended manual user settings, see
213H
Table 56 and
214H
Figure 22 for NTSC; see
215H
Table 57 and
216H
Figure 27 for PAL.
HVSTIM Horizontal VS Timing, Address 0x31[3]
The HVSTIM bit allows the user to select where the VS signal is
being asserted within a line of video. Some interface circuitry
can require VS to go low while HS is low.
When HVSTIM is 0 (default), the start of the line is relative
to HSE.
When HVSTIM is 1, the start of the line is relative to HSB.
VSBHO VS Begin Horizontal Position Odd,
Address 0x32[7]
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
When VSBHO is 0 (default), the VS pin goes high at the middle
of a line of video (odd field).
When VSBHO is 1, the VS pin changes state at the start of a line
(odd field).
VSBHE VS Begin Horizontal Position Even,
Address 0x32[6]
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state when
only HS is high/low.
When VSBHE is 0, the VS pin goes high at the middle of a line
of video (even field).
When VSBHE is 1 (default), the VS pin changes state at the start
of a line (even field).
VSEHO VS End Horizontal Position Odd,
Address 0x33[7]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
When VSEHO is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (odd field).
When VSEHO is 1, the VS pin changes state at the start of a line
(odd field).
VSEHE VS End Horizontal Position Even,
Address 0x33[6]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to change state only
when HS is high/low.
When VSEHE is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (even field).
When VSEHE is 1, the VS pin changes state at the start of a line
(even field).
PVS Polarity VS, Address 0x37[5]
The polarity of the VS pin can be inverted using the PVS bit.
When PVS is 0 (default), VS is active high.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-213-IY-F3 | CONVERTER MOD DC/DC 24V 50W |
| VE-23J-IY-F2 | CONVERTER MOD DC/DC 36V 50W |
| LF10WBR-12P | CONN RCPT WATERPROOF 12POS MALE |
| VI-212-IY-F3 | CONVERTER MOD DC/DC 15V 50W |
| VE-B7N-IX-B1 | CONVERTER MOD DC/DC 18.5V 75W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7183KST | 制造商:Analog Devices 功能描述:Video Decoder 2ADC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:VIDEO DECODER I.C. - Bulk |
| ADV7184 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
| ADV7184BSTZ | 功能描述:IC DECODER VID SDTV MULTI 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7185 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
| ADV7185KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。