參數(shù)資料
型號(hào)： ADV7183BKSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 56/100頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO DECODER NTSC 80-LQFP
產(chǎn)品培訓(xùn)模塊： Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝： 1
類型： 視頻解碼器
應(yīng)用： 投影儀，錄音機(jī)，安全
電壓 - 電源，模擬： 3.15 V ~ 3.45 V
電壓 - 電源，數(shù)字： 1.65 V ~ 2 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 788 (CN2011-ZH PDF)
ADV7183B
Rev. B | Page 59 of 100
PIXEL PORT CONFIGURATION
The ADV7183B has a very flexible pixel port that can be confi-
gured in a variety of formats to accommodate downstream ICs.
256H
Table 79 and
257H
Table 80 summarize the various functions that the
ADV7183B’s pins can have in different modes of operation.
The ordering of components (for example, Cr versus Cb,
CHA/B/C) can be changed. Refer to the section.
258H
Table 79
indicates the default positions for the Cr/Cb components.
OF_SEL[3:0] Output Format Selection, Address 0x03[5:2]
The modes in which the ADV7183B pixel port can be onfigured
are under the control of OF_SEL[3:0]. See
259H
Table 80 for details.
The default LLC frequency output on the LLC1 pin is
approximately 27 MHz. For modes that operate with a nominal
data rate of 13.5 MHz (0001, 0010), the clock frequency on the
LLC1 pin stays at the higher rate of 27 MHz. For information
on outputting the nominal 13.5 MHz clock on the LLC1 pin, see
the
260H
PAD_SEL[2:0], Address 0x8F[6:4] section.
SWPC Swap Pixel Cr/Cb, Address 0x27[7]
This bit allows Cr and Cb samples to be swapped.
When SWPC is 0 (default), no swapping is allowed.
When SWPC is 1, the Cr and Cb values can be swapped.
PAD_SEL[2:0], Address 0x8F[6:4]
This I2C write allows the user to select between the LLC1
(nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).
The LLC2 signal is useful for LLC2-compatible wide bus
(16-bit) output modes. See the
261H
OF_SEL[3:0] Output Format
Selection, Address 0x03[5:2] section for additional information.
The LLC2 signal and data on the data bus are synchronized. By
default, the rising edge of LLC1/LLC2 is aligned with the Y
data; the falling edge occurs when the data bus holds C data.
The polarity of the clock, and therefore the Y/C assignments to
the clock edges, can be altered by using the Polarity LLC pin.
When LLC_PAD_SEL[2:0] is 000 (default), the output is
nominally 27 MHz LLC on the LLC1 pin.
When LLC_PAD_SEL[2:0] is 101, the output is nominally
13.5 MHz LLC on the LLC1 pin.
Table 79. P15 to P0 Output/Input Pin Mapping
Data Port Pins P[15:0]
Format, and Mode
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Video Out, 8-Bit, 4:2:2
YCrCb[7:0] OUT
Video Out, 16-Bit, 4:2:2
Y[7:0] OUT
CrCb[7:0] OUT
Table 80. Standard Definition Pixel Port Modes
P[15: 0]
OF_SEL[3:0]
Format
P[15:8]
P[7: 0]
0010
16-bit @ LLC2 4:2:2
Y[7:0]
CrCb[7:0]
0011 (default)
8-bit @ LLC1 4:2:2 (default)
YCrCb[7:0] (default)
Three-state
0110-1111
Reserved
Reserved. Do not use.
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