參數(shù)資料
型號： ADV7183BKSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 82/100頁
文件大?。?/td> 0K
描述： IC VIDEO DECODER NTSC 80-LQFP
產(chǎn)品培訓(xùn)模塊： Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝： 1
類型： 視頻解碼器
應(yīng)用： 投影儀，錄音機(jī)，安全
電壓 - 電源，模擬： 3.15 V ~ 3.45 V
電壓 - 電源，數(shù)字： 1.65 V ~ 2 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 788 (CN2011-ZH PDF)
ADV7183B
Rev. B | Page 82 of 100
Bits
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
0
1 line of video.
0
1
2 lines of video.
0
1
0
5 lines of video.
0
1
10 lines of video.
1
0
100 lines of video.
1
0
1
500 lines of video.
1
0
1000 lines of video.
CIL[2:0]. Count-into-lock determines
the number of lines the system must
remain in lock before showing a
locked status.
1
100000 lines of video.
0
1 line of video.
0
1
2 lines of video.
0
1
0
5 lines of video.
0
1
10 lines of video.
1
0
100 lines of video.
1
0
1
500 lines of video.
1
0
1000 lines of video.
COL[2:0]. Count-out-of-lock
determines the number of lines the
system must remain out-of-lock
before showing a lost-locked status.
1
100000 lines of video.
0
Over field with vertical
info.
SRLS. Select raw lock signal. Selects
the determination of the lock status.
1
Line-to-line evaluation.
0
Lock status set only by
horizontal lock.
0x51
Lock
Count
FSCLE. Fsc lock enable.
1
Lock status set by
horizontal lock and
subcarrier lock.
Reserved
0
Set to default.
0
LLC1 (nominal 27 MHz)
selected out on LLC1 pin.
LLC_PAD_SEL[2:0]. Enables manual
selection of clock for LLC1 pin.
1
0
1
LLC2 (nominally
13.5 MHz) selected out on
LLC1 pin.
For 16-bit 4:2:2 out,
OF_SEL[3:0] = 0010.
0x8F
Free Run
Line
Length 1
Reserved
0
Set to default.
0
No WSS detected.
WSSD. Screen signaling detected.
1
WSS detected.
0
No CCAP signals
detected.
CCAPD. Closed caption data.
1
CCAP sequence detected.
0
No EDTV sequence
detected.
EDTVD. EDTV sequence.
1
EDTV sequence detected.
0
No CGMS transition
detected.
CGMSD. CGMS sequence.
1
CGMS sequence
decoded.
0x90
VBI Info
(Read Only)
Reserved.
x
Read only status bits.
0x91
WSS1
(Read Only)
WSS1[7:0]
Wide screen signaling data.
x
0x92
WSS2
(Read Only)
WSS2[7:0]
Wide screen signaling data.
x
WSS2[7:6] are
undetermined.
0x93
WSS2
(Read Only)
WSS2[7:0]
Wide screen signaling data.
x
0x94
EDTV2
(Read Only)
EDTV2[7:0]
EDTV data register.
x
0x95
EDTV3
(Read Only)
EDTV3[7:0]
EDTV data register.
x
EDTV3[7:6] are
undetermined.
EDTV3[5] is reserved
for future use.
0x96
CGMS1
(Read Only)
CGMS1[7:0]
CGMS data register.
x
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