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參數(shù)資料
| 型號(hào)： | ADV612 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 視頻Codec |
| 英文描述： | Closed Circuit TV Digital Video Codec(閉路電視數(shù)字視頻編碼譯碼器) |
| 中文描述： | 閉路電視數(shù)字視頻編解碼器（閉路電視數(shù)字視頻編碼譯碼器） |
| 文件頁數(shù)： | 42/48頁 |
| 文件大?。?/td> | 1085K |
| 代理商： | ADV612 |
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ADV611/ADV612
–42–
REV. PrA
PRELMNARY
Figure 34. Host (Compressed Data) Read Transfer Timing
TECHNCAL
DATA
Host Interface (Compressed Data) Register Timing
The diagrams in this section show transfer timing for host read and write transfers to the ADV611/ADV612’s Compressed Data
register. Accesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and
Interrupt Mask/Status registers. For information on access timing for the other registers, see the Host Interface (Indirect Address
,
Indirect Register Data, and Interrupt Mask/Status) Register Timing section. Also note that as long as your system observes the
RD
or
WR
signal assertion timing, your system does
NOT
have to wait for the
ACK
signal between new compressed data addresses.
Table XXVIII. Host (Compressed Data) Read Timing Parameters
Parameter
Description
Min
Max
Unit
t
RD_CD_RDC
t
RD_CD_PWA
t
RD_CD_PWD
t
ADR_CD_RDS
t
ADR_CD_RDH
t
DATA_CD_RDD
t
DATA_CD_RDOH
t
ACK_CD_RDD
t
ACK_CD_RDOH
RD
Signal, Compressed Data Direct Register, Read Cycle Time
RD
Signal, Compressed Data Direct Register, Pulsewidth Asserted
RD
Signal, Compressed Data Direct Register, Pulsewidth Deasserted
ADR Bus, Compressed Data Direct Register, Read Setup
ADR Bus, Compressed Data Direct Register, Read Hold (at 27 MHz VCLK)
DATA Bus, Compressed Data Direct Register, Read Delay
DATA Bus, Compressed Data Direct Register, Read Output Hold
ACK
Signal, Compressed Data Direct Register, Read Delay
ACK
Signal, Compressed Data Direct Register, Read Output Hold
28
10
10
2
2
N/A
18
N/A
9
N/A
N/A
N/A
N/A
N/A
10
N/A
18
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
(I) ADR,
BE
,
CS
(I)
RD
(O) DATA
(O)
ACK
VALID
VALID
VALID
t
ADR CD RDS
t
DATA CD RDD
t
ACK CD RDD
t
ACK CD RDOH
t
DATA CD RDOH
t
ADR CD RDH
t
RD CD RDC
t
RD CD PWA
t
RD CD PWD
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