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參數(shù)資料
| 型號(hào)： | ADV612 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 視頻Codec |
| 英文描述： | Closed Circuit TV Digital Video Codec(閉路電視數(shù)字視頻編碼譯碼器) |
| 中文描述： | 閉路電視數(shù)字視頻編解碼器（閉路電視數(shù)字視頻編碼譯碼器） |
| 文件頁數(shù)： | 31/48頁 |
| 文件大?。?/td> | 1085K |
| 代理商： | ADV612 |
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ADV611/ADV612
–31–
REV. PrA
Devices has not actually built or tested these circuits.
Using the Philips SAA7111 Video Decoder
The SAA7111 example circuit, which appears in Figure 17, is
used in this configuration on the ADV611/ADV612 CCTVPIPE
demonstration board.
TECHNCAL
family can be used. The user must select the part needed based
on the requirements of the application. Because the Raytheon
part does not include the A/Ds, an external A/D is necessary in
this design (or a pair of A/Ds for Svideo).
The part can be used in CCIR-656 (D1) mode for a zero con-
trol signal interface. Special attention must be paid to the video
output modes in order to get the right data to the right pins (see
the following diagram).
Note that the circuit in Figure 19 has not been built or tested.
(MODE 0 & SLAVE MODE)
(CCIR-656 MODE)
XTAL
10k
V
150
V
VCLK
XTAL
ADV611/ADV612
VCLKO
CLOCK
P7–P0
ALSB
ADV7175
BLANK
VDATA (7:0)
Figure 18. ADV611/ADV612 and ADV7175 Example
Interfacing Block Diagram
Using the Raytheon TMC22153 Video Decoder
Raytheon has a whole family of video parts. Any member of the
MODE SET TO:
CDEC = 1
YUVT
F422
= 1
= X
TMC22153
Y(2:9)
CLOCK
XTAL
VCLK
VCLK
VDATA (0:7)
ADV611/ADV612
(CCIR-656 & SLAVE MODE)
Figure 19. ADV611/ADV612 and TMC22153 Example
CCIR-656 Mode Interface
FL0
FL1
ADR0
ADR1
D8–D23
D0–D15
D16–D31
PF4
PF5
FL2
CS/
RD/
RD/
LCODE
HIRQ/
IRQ2
IRQL1
A0–A8
D0–D15
RAS
CAS
A0–A8
DQ1–DQ16
RAS
CAS
OE
THE ADSP-2185 INTERNAL CLOCK RATE
DOUBLE THE INPUT CLOCK
*THE INPUT CLOCK RATE = 1/2 OF THE INTERNAL
CLOCK RATE, RANGING FROM 12 TO 21MHz
ADV611/ADV612
ADSP-2185
DRAM
(256K
3
16-BIT)
WEL
WEH
TOSHIBA TC514265DJ/DZ/DFT-60
NEC
m
PD424210ALE-60
NEC
PD42S4210ALE-60
HITACHI
HM514265CJ-60
ANY DRAM USED WITH THE ADV611/ADV612
MUST MEET THE MINIMUM SPECIFICATIONS
OUTLINED FOR THE HYPER MODE DRAMS
LISTED
WR/
WR/
BE2–BE3/
WE
VCLK
VDATA [0–7]
LLC
XTAL
SAA7111
Y[0–7]
COMPOSITE VIDEO INPUT
BE0–BE1/
27MHz PAL OR NTSC
24.576MHz
XTAL
Figure 16. Alternate Stand-Alone Application Design
Using the ADV611/ADV612 In Stand-Alone Applications
Figure 16 shows the ADV611/ADV612 in a noncomputer based
applications. Here, an ADSP-2185 digital signal processor
provides Host control and BW calculation services. Note that
all control and BW operations occur over the host interface in
this design.
Connecting the ADV611/ADV612 to Popular Video Decoders
and Encoders
The following circuits are recommendations only. Analog
XTAL
(CCIR-656 MODE)
SAA7111
Y(0:7)
LLC
XTAL
VCLK
ADV611/ADV612
VDATA (0:7)
Figure 17. ADV611/ADV612 and SAA7111 Example
Interfacing Block Diagram
Using the Analog Devices ADV7175 Video Encoder
Because the ADV7175 has a CCIR-656 interface, it connects
directly with the ADV611/ADV612 without “glue” logic. Note
that the ADV7175 can only be used at CCIR-601 sampling
rates.
The ADV7175 example circuit, which appears in Figure 18, is
used in this configuration on the ADV611/ADV612 CCTVPIPE
demonstration board.
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