參數(shù)資料
型號(hào)： ADV612
廠商： Analog Devices, Inc.
元件分類： 視頻Codec
英文描述： Closed Circuit TV Digital Video Codec(閉路電視數(shù)字視頻編碼譯碼器)
中文描述： 閉路電視數(shù)字視頻編解碼器（閉路電視數(shù)字視頻編碼譯碼器）
文件頁數(shù)： 40/48頁
文件大小： 1085K
代理商： ADV612
ADV611/ADV612
–40–
REV. PrA
VALID
TECHNCAL
VALID
Host Interface (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Register Timing
The diagrams in this section show transfer timing for host read and write accesses to all of the ADV611/ADV612’s direct registers,
except the Compressed Data register. Accesses to the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers
are
slower
than access timing for the Compressed Data register. For information on access timing for the Compressed Data direct
register, see the Host Interface (Compressed Data) Register Timing section. Note that for accesses to the Indirect Address, Indirect
Register Data and Interrupt Mask/Status registers, your system
MUST
observe
ACK
and
RD
or
WR
assertion timing.
Table XXVI. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Read Timing Parameters
Parameter
Description
Min
N/A
1
N/A
1
5
2
2
N/A
13
48.7
4
8.6
11
Max
Unit
t
RD_D_RDC
t
RD_D_PWA
t
RD_D_PWD
t
ADR_D_RDS
t
ADR_D_RDH
t
DATA_D_RDD
t
DATA_D_RDOH
t
RD_D_WRT
t
ACK_D_RDD
t
ACK_D_RDOH
RD
Signal, Direct Register, Read Cycle Time (at 27 MHz VCLK)
RD
Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)
RD
Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)
ADR Bus, Direct Register, Read Setup
ADR Bus, Direct Register, Read Hold
DATA Bus, Direct Register, Read Delay
DATA Bus, Direct Register, Read Output Hold (at 27 MHz VCLK)
WR
Signal, Direct Register, Read-to-Write Turnaround (at 27 MHz VCLK)
ACK
Signal, Direct Register, Read Delayed (at 27 MHz VCLK)
ACK
Signal, Direct Register, Read Output Hold (at 27 MHz VCLK)
N/A
N/A
N/A
N/A
N/A
171.6
2, 3
N/A
N/A
287.1
5, 6
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
RD
input must be asserted (low) until ACK is asserted (low).
2
Maximum t
DATA_D_RDD
varies with VCLK according to the formula: t
DATA_D_RDD
(MAX)
= 4 (VCLK Period) +16.
3
During STATS_R deasserted (low) conditions, t
DATA_D_RDD
may be as long as 52 VCLK periods.
4
Minimum t
RD_D_WRT
varies with VCLK according to the formula: t
RD_D_WRT
(MIN)
= 1.5 (VCLK Period) –4.1.
5
Maximum t
ACK_D_RDD
varies with VCLK according to formula: t
ACK_D_RDD (MAX)
= 7 (VCLK Period) +14.8.
6
During STATS_R deasserted (low) conditions, t
ACK_D_RDD
may be as long as 52 VCLK periods.
VALID
VALID
(I) ADR,
BE
,
CS
(I)
RD
(O) DATA
(O)
ACK
(I)
WR
t
ADR D RDS
t
ACK D RDOH
t
RD D RDC
t
RD D PWA
t
RD D PWD
t
ADR D RDH
t
DATA D RDD
t
DATA D RDOH
t
RD D WRT
t
ACK D RDD
Figure 32. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Read Transfer Timing
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