參數(shù)資料
型號(hào)： ADV612
廠商： Analog Devices, Inc.
元件分類(lèi)： 視頻Codec
英文描述： Closed Circuit TV Digital Video Codec(閉路電視數(shù)字視頻編碼譯碼器)
中文描述： 閉路電視數(shù)字視頻編解碼器（閉路電視數(shù)字視頻編碼譯碼器）
文件頁(yè)數(shù)： 11/48頁(yè)
文件大小： 1085K
代理商： ADV612
ADV611/ADV612
–11–
REV. PrA
condition coming true, they cannot be read or tested for stable level true conditions multiple times.
The FIFOSRQ bit is not sticky. This bit can be polled to monitor for a FIFOSRQ true condition. Note: Enable this monitoring by
using the FIFOSRQ bit and correctly programming DSL and ESL fields within the FIFO control registers.
[0]
CCIR-656 Error in CCIR-656 data stream,
CCIRER
. This read only status bit indicates the following:
0
No CCIR-656 Error condition,
reset value
1
Unrecoverable error in CCIR-656 data stream (missing sync codes)
[1]
Statistics Ready,
STATSR
. This read only status bit indicates the following:
0
No Statistics Ready condition,
reset value
(STATS_R pin LO)
1
Statistics Ready for BW calculator (STATS_R pin HI)
[2]
Last Code Read,
LCODE
. This read only status bit indicates the last compressed data word for field will be
retrieved from the FIFO on the next read from the host bus.
0
No Last Code condition,
reset value
(LCODE pin LO)
1
Next read retrieves last word for field in FIFO (LCODE pin HI)
[3]
FIFO Service Request,
FIFOSRQ
. This read only status bit indicates the following:
0
No FIFO Service Request condition,
reset value
(FIFO_SRQ pin LO)
1
FIFO is nearly full (encode) or nearly empty (decode) (FIFO_SRQ pin HI)
[4]
FIFO Error,
FIFOERR
. This condition indicates that the host has been unable to keep up with the ADV611/ADV612’s com-
compressed data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted
until MERR indicates that the DRAM has also overflowed. If this condition occurs during decode, the video output will be
corrupted. If the system overflows the FIFO (disregarding a FIFOSTP condition) with too many writes in decode mode,
FIFOERR is asserted. This read only status bit indicates the following:
0
No FIFO Error condition,
reset value
(FIFO_ERR pin LO)
1
FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)
TECHNCAL
ADV611/ADV612 REGISTER DESCRIPTIONS
Indirect Address Register
Direct (Write) Register Byte Offset 0x00.
This register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All
indirect write registers are 16 bits wide. The address in this register is auto-incremented on each subsequent access of the indirect
data register. This capability enhances I/O performance during modes of operation where the host is calculating Bin Width controls.
[15:0]
Indirect Address Register,
IAR[15:0]
. Holds a 16-bit value (index) that selects the indirect register to read or write through
the indirect data register (undefined at reset)
[31:16] Reserved (undefined read/write zero)
Indirect Register Data
Direct (Read/Write) Register Byte Offset 0x04
This register holds a 16-bit value read or written from or to the indirect register indexed by the Indirect Address Register.
[15:0]
Indirect Register Data,
IRD[15:0]
. A 16-bit value read or written to the indexed indirect register. Undefined at reset.
[31:16] Reserved (undefined read/write zero)
Compressed Data Register
Direct (Read/Write) Register Byte Offset 0x08
This register holds a 32-bit sequence from the compressed video bitstream. This register is buffered by a 512 position, 32-bit FIFO.
For Word (16-bit) accesses, access Word0 (Byte 0 and Byte 1) then Word1 (Byte 2 and Byte 3) for correct auto-increment. For a
description of the data sequence, see the Compressed Data Stream Definition section.
[31:0]
Compressed Data Register,
CDR[31:0]
. 32-bit value containing compressed video stream data. At reset, contents undefined.
Interrupt Mask / Status Register
Direct (Read/Write) Register Byte Offset 0x0C
This 16-bit register contains interrupt mask and status bits that control the state of the ADV611/ADV612’s
HIRQ
pin. With the
seven mask bits (IE_LCODE, IE_STATSR, IE_FIFOSTP, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR); select the con-
ditions that are ORed together to determine the output of the
HIRQ
pin.
Six of the status bits (LCODE, STATSR, FIFOSTP, MERR, FIFOERR, CCIRER) indicate active interrupt conditions and are
sticky bits that stay set until read. Because sticky status bits are cleared when read, and these bits are set on the positive edge of the
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