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參數(shù)資料
| 型號： | ADV612 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 視頻Codec |
| 英文描述： | Closed Circuit TV Digital Video Codec(閉路電視數(shù)字視頻編碼譯碼器) |
| 中文描述： | 閉路電視數(shù)字視頻編解碼器（閉路電視數(shù)字視頻編碼譯碼器） |
| 文件頁數(shù)： | 30/48頁 |
| 文件大小： | 1085K |
| 代理商： | ADV612 |
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ADV611/ADV612
–30–
REV. PrA
PRELMNARY
WR
DECODE
2
STATS R
HIRQ
TECHNCAL
DATA
APPLYING THE ADV611/ADV612
This section includes the following topics:
Using the ADV611/ADV612 in computer applications
Using the ADV611/ADV612 in stand-alone applications
Configuring the host interface for 16- or 32-bit data paths
Connecting the video interface to popular video encoders and
decoders
Getting the most out of the ADV611/ADV612
The following Analog Devices products should be considered in
ADV611/ADV612 designs:
ADV7175/ADV7176—Digital YUV to analog composite
video encoder
AD722—Analog RGB to analog composite video encoder
AD1843—Audio codec with embedded video synchronization
ADSP-21xx—Family of fixed-point digital signal processors
AD8xxx—Family of video operational amplifiers
Using the ADV611/ADV612 in Computer Applications
Many key features of the ADV611/ADV612 were driven by the
demanding cost and performance requirements of computer
applications. The following ADV611/ADV612 features provide
key advantages in computer applications, such as the one in
Figure 15.
Host Interface
The 512 double word FIFO provides necessary buffering of
compressed digital video to deal with PCI bus latency.
Low Cost External DRAM
Unlike many other real-time compression solutions, the
ADV611/ADV612 does not require expensive external
SRAM transform buffers or VRAM frame stores.
A2
A3
D0–D7
D8–D15
D16–D23
D24–D31
A28
A29
A30
A31
HOST BUS
RD
DECODE
1
VCLK
VDATA [0–7]
LLC
XTAL
SAA7111
27MHz PAL OR NTSC
ADR0
ADR1
DQ0–DQ7
DQ8–DQ15
DQ16–DQ23
DQ24–DQ31
CS
LCODE
ACK
24.576MHz
XTAL
A0–A8
D0–D15
RAS
CAS
A0–A8
DQ1–DQ16
RAS
CAS
OE
NOTE:
DECODE
1
ASSERTS CS
~
ON THE
ADV611/ADV612 FOR HOST ADDRESSES
0X4000,0000 THROUGH 0X4000,0013
DECODE
IS HOST-SPECIFIC
ADV611/ADV612
DRAM
(256K
3
16-BIT)
COMPOSITE VIDEO INPUT
VCLKO
TOSHIBA TC514265DJ/DZ/DFT-60
NEC
m
PD424210ALE-60
NEC
m
PD42S4210ALE-60
HM514265CJ-60
ANY DRAM USED WITH THE ADV611/ADV612
MUST MEET THE MINIMUM SPECIFICATIONS
OUTLINED FOR THE HYPER MODE DRAMS
LISTED
FIFO SRQ
FIFO ERR
FIFO STP
Y[0–7]
BE0–BE1
BE2–BE3
RD
WR
WE
WEL
WEH
Figure 15. A Suggested PC Application Design
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