參數(shù)資料
型號(hào)： ADV612
廠商： Analog Devices, Inc.
元件分類： 視頻Codec
英文描述： Closed Circuit TV Digital Video Codec(閉路電視數(shù)字視頻編碼譯碼器)
中文描述： 閉路電視數(shù)字視頻編解碼器（閉路電視數(shù)字視頻編碼譯碼器）
文件頁數(shù)： 41/48頁
文件大?。?/td> 1085K
代理商： ADV612
ADV611/ADV612
–41–
REV. PrA
PRELMNARY
TECHNCAL
DATA
Table XXVII. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Write Timing Parameters
Parameter
Description
Min
N/A
1
N/A
1
5
2
2
–20
0
35.6
2
8.6
11
Max
Unit
t
WR_D_WRC
t
WR_D_PWA
t
WR_D_PWD
t
ADR_D_WRS
t
ADR_D_WRH
t
DATA_D_WRS
t
DATA_D_WRH
t
WR_D_RDT
t
ACK_D_WRD
t
ACK_D_WROH
WR
Signal, Direct Register, Write Cycle Time (at 27 MHz VCLK)
WR
Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)
WR
Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)
ADR Bus, Direct Register, Write Setup
ADR Bus, Direct Register, Write Hold
DATA Bus, Direct Register, Write Setup
DATA Bus, Direct Register, Write Hold
WR
Signal, Direct Register, Read Turnaround (After a Write) (at 27 MHz VCLK)
ACK
Signal, Direct Register, Write Delay (at 27 MHz VCLK)
ACK
Signal, Direct Register, Write Output Hold
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
182.1
3, 4
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
WR
input must be asserted (low) until ACK is asserted (low).
2
Minimum t
WR_D_RDT
varies with VCLK according to the formula: t
WR_D_RDT (MIN)
= 0.8 (VCLK Period) +7.4.
3
Maximum t
varies with VCLK according to the formula: t
= 4.3 (VCLK Period) +14.8.
4
During STATS_R deasserted (low) conditions, t
ACK_D_WRD
may be as long as 52 VCLK periods.
VALID
VALID
VALID
VALID
(I) ADR,
BE
,
CS
(I)
WR
(I) DATA
(O)
ACK
(I)
RD
t
ADR D WRS
t
DATA D WRS
t
WR D WRC
t
WR D PWA
t
WR D PWD
t
ADR D WRH
t
DATA D WRH
t
ACK D WRD
t
WR D RDT
Figure 33. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Write Transfer Timing
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