參數(shù)資料
型號(hào)： ADUC831BSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 46/76頁(yè)
文件大?。?/td> 0K
描述： IC MCU 62K FLASH ADC/DAC 52MQFP
標(biāo)準(zhǔn)包裝： 800
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 帶卷 (TR)
配用： EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START
REV. 0
–50–
ADuC831
User configuration and control of all Timer operating modes is achieved via three SFRs:
TMOD, TCON
Control and configuration for Timers 0 and 1.
T2CON
Control and configuration for Timer 2.
TMOD
Timer/Counter 0 and 1 Mode Register
SFR Address
89H
Power-On Default Value
00H
Bit Addressable
No
Table XIX. TMOD SFR Bit Designations
Bit
Name
Description
7
Gate
Timer 1 Gating Control.
Set by software to enable timer/counter 1 only while
INT1 pin is high and TR1 control bit is set.
Cleared by software to enable Timer 1 whenever TR1 control bit is set.
6
C/T
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select timer operation (input from internal system clock).
5M1Timer 1 Mode Select Bit 1 (Used with M0 Bit).
4M0Timer 1 Mode Select Bit 0.
M1
M0
00
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
01
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
10
8-Bit Auto-Reload Timer/Counter. TH1 holds a value which is to be
reloaded into TL1 each time it overflows.
11
Timer/Counter 1 Stopped.
3
Gate
Timer 0 Gating Control.
Set by software to enable timer/counter 0 only while
INT0 pin is high and TR0 control bit is set.
Cleared by software to enable Timer 0 whenever TR0 control bit is set.
2
C/T
Timer 0 Timer or Counter Select Bit.
Set by software to select counter operation (input from T0 pin).
Cleared by software to select timer operation (input from internal system clock).
1M1Timer 0 Mode Select Bit 1.
0M0Timer 0 Mode Select Bit 0.
M1
M0
00
TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler.
01
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
10
8-Bit Auto-Reload Timer/Counter. TH0 holds a value which is to
be reloaded into TL0 each time it overflows.
11
TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits.
TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
Timers/Counters
The ADuC831 has three 16-bit Timer/Counters: Timer 0,
Timer 1, and Timer 2. The Timer/Counter hardware has been
included on-chip to relieve the processor core of the overhead
inherent in implementing Timer/Counter functionality in soft-
ware. Each Timer/Counter consists of two 8-bit registers THx
and TLx (x = 0, 1, and 2). All three can be configured to oper-
ate either as timers or event counters.
In “Timer” function, the TLx register is incremented every
machine cycle. Thus, one can think of it as counting machine
cycles. Since a machine cycle consists of 12 core clock periods,
the maximum count rate is 1/12 of the core clock frequency.
In “Counter” function, the TLx register is incremented by a 1-to-0
transition at its corresponding external input pin, T0, T1, or T2.
In this function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in one
cycle and a low in the next cycle, the count is incremented. The
new count value appears in the register during S3P1 of the cycle
following the one in which the transition was detected. Since it
takes two machine cycles (24 core clock periods) to recognize a
1-to-0 transition, the maximum count rate is 1/24 of the core
clock frequency. There are no restrictions on the duty cycle of the
external input signal, but to ensure that a given level is sampled
at least once before it changes, it must be held for a minimum of
one full machine cycle.
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