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參數(shù)資料
| 型號： | ADUC831BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標準包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START |
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REV. 0
–24–
ADuC831
Configuring the ADC
The ADuC831’s successive approximation ADC is driven by a
divided down version of the master clock. To ensure adequate
ADC operation, this ADC clock must be between 400 kHz and
6 MHz, and optimum performance is obtained with ADC clock
between 400 kHz and 4.5 MHz. Frequencies within this range
can easily be achieved with master clock frequencies from
400 kHz to well above 16 MHz with the four ADC clock divide
ratios to choose from. For example, with a 12 MHz master
clock, set the ADC clock divide ratio to 4 (i.e., ADCCLK =
MCLK/4 = 3 MHz) by setting the appropriate bits in
ADCCON1 (ADCCON1.5 = 1, ADCCON1.4 = 0).
The total ADC conversion time is 15 ADC clocks, plus 1 ADC
clock for synchronization, plus the selected acquisition time
(1, 2, 3, or 4 ADC clocks). For the example above, with three
clocks acquisition time, total conversion time is 19 ADC clocks
(or 6.3
s for a 3 MHz ADC clock).
In continuous conversion mode, a new conversion begins each
time the previous one finishes. The sample rate is then simply
the inverse of the total conversion time described above. In the
example above, the continuous conversion mode sample rate
would be 157.8 kHz.
If using the temperature sensor as the ADC input, the ADC
should be configured to use an ADCCLK of MCLK/16 and
four acquisition clocks.
Increasing the conversion time on the temperature monitor
channel improves the accuracy of the reading. To further
improve the accuracy, an external reference with low tempera-
ture drift should also be used.
ADC DMA Mode
The on-chip ADC has been designed to run at a maximum
conversion speed of 4
s (247 kHz sampling rate). When con-
verting at this rate, the ADuC831 MicroConverter has 4
s to
read the ADC result and store the result in memory for further
postprocessing, otherwise the next ADC sample could be lost.
In an interrupt driven routine the MicroConverter would also
have to jump to the ADC Interrupt Service routine, which will
also increase the time required to store the ADC results. In
applications where the ADuC831 cannot sustain the interrupt
rate, an ADC DMA mode is provided.
To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be
set. This allows the ADC results to be written directly to a
16 MByte external static memory SRAM (mapped into data
memory space) without any interaction from the ADuC831
core. This mode allows the ADuC831 to capture a contiguous
sample stream at full ADC update rates (247 kHz).
A Typical DMA Mode Configuration Example
To set the ADuC831 into DMA mode a number of steps must
be followed:
1. The ADC must be powered down. This is done by ensuring
MD1 and MD0 are both set to 0 in ADCCON1.
2. The DMA address pointer must be set to the start address of
where the ADC results are to be written. This is done by
writing to the DMA mode address pointers DMAL, DMAH,
and DMAP. DMAL must be written to first, followed by
DMAH, and then by DMAP.
3. The external memory must be preconfigured. This consists
of writing the required ADC channel IDs into the top four
bits of every second memory location in the external SRAM
starting at the first address specified by the DMA address
pointer. As the ADC DMA mode operates independent from
the ADuC831 core, it is necessary to provide it with a stop
command. This is done by duplicating the last channel ID to
be converted followed by “1111” into the next channel selec-
tion field. A typical preconfiguration of external memory is
as follows.
11
1
00
1
00
1
10
0
01
0
1
00
1
0
00000AH
000000H
STOP COMMAND
REPEAT LAST CHANNEL
FOR A VALID STOP
CONDITION
CONVERT ADC CH#3
CONVERT TEMP SENSOR
CONVERT ADC CH#5
CONVERT ADC CH#2
Figure 14. Typical DMA External Memory Preconfiguration
4. The DMA is initiated by writing to the ADC SFRs in the
following sequence:
a. ADCCON2 is written to enable the DMA mode, i.e.,
MOV ADCCON2, #40H; DMA mode enabled.
b. ADCCON1 is written to configure the conversion time and
power-up of the ADC. It can also enable Timer 2 driven
conversions or external triggered conversions if required.
c. ADC conversions are initiated. This is done by starting
single conversions, starting Timer 2 running for Timer 2
conversions or by receiving an external trigger.
When the DMA conversions are completed, the ADC interrupt
bit ADCI, is set by hardware and the external SRAM contains
the new ADC conversion results as shown below. It should be
noted that no result is written to the last two memory locations.
When the DMA mode logic is active, it takes the responsibility of
storing the ADC results away from both the user and ADuC831
core logic. As it writes the results of the ADC conversions to
external memory, it takes over the external memory interface
from the core. Thus, any core instructions that access the external
memory while DMA mode is enabled will not get access to it. The
core will execute the instructions and they will take the same time
to execute but they will not gain access to the external memory.
NO CONVERSION
RESULT WRITTEN HERE
CONVERSION RESULT
FOR ADC CH#3
CONVERSION RESULT
FOR TEMP SENSOR
CONVERSION RESULT
FOR ADC CH#5
CONVERSION RESULT
FOR ADC CH#2
11
00
11
00
11
10
0
01
0
1
00
10
00000AH
000000H
STOP COMMAND
Figure 15. Typical External Memory Configuration
Post ADC DMA Operation
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