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參數(shù)資料
| 型號： | ADUC831BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 62KB（62K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START |
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REV. 0
ADuC831
–37–
MODE 4: Dual NRZ 16-Bit
-
DAC
Mode 4 provides a high speed PWM output similar to that of a
-
DAC. Typically, this mode will be used with the PWM
clock equal to 16 MHz.
In this mode P2.6 and P2.7 are updated every PWM clock
(62 ns in the case of 16 MHz). Over any 65536 cycles (16 bit
PWM) PWM0 (P2.6) is high for PWM0H/L cycles and low for
(65536 - PWM0H/L) cycles. Similarly PWM1 (P2.7) is high for
PWM1H/L cycles and low for (65536 - PWM1H/L) cycles.
For example, if PWM1H was set to 4010H (slightly above one
quarter of FS) then typically P2.7 will be low for three clocks
and high for one clock (each clock is approximately 80 ns). Over
every 65536 clocks the PWM will compensate for the fact that
the output should be slightly above one quarter of full scale by
having a high cycle followed by only two low cycles.
16MHz
16-BIT
62 s
0
16-BIT
CARRY OUT AT P2.6
PWM0H/L = C000H
PWM1H/L = 4000H
00
1
00
0
LATCH
0
11
1
0
62 s
CARRY OUT AT P2.7
Figure 30. PWM Mode 4
For faster DAC outputs (at lower resolution) write 0s to the
LSBs that are not required. If for example only 12-bit perfor-
mance is required then write 0s to the 4LSBs. This means that a
12-bit accurate
Σ- DAC output can occur at 3.906 kHz. Simi-
larly, writing 0s to the 8 LSBs gives an 8-bit accurate
Σ- DAC
output at 62 kHz.
MODE 5: Dual 8-Bit PWM
In Mode 5, the duty cycle of the PWM outputs and the resolu-
tion of the PWM outputs are individually programmable. The
maximum resolution of the PWM output is eight bits. The
output resolution is set by the PWM1L and PWM1H SFRs for
the P2.6 and P2.7 outputs, respectively. PWM0L and PWM0H
sets the duty cycles of the PWM outputs at P2.6 and P2.7, respec-
tively. Both PWMs have same clock source and clock divider.
P2.7
P2.6
PWM COUNTERS
PWM1H
0
PWM1L
PWM0H
PWM0L
Figure 31. PWM Mode 5
MODE 6: Dual RZ 16-Bit
-
DAC
Mode 6 provides a high speed PWM output similar to that of a
-
DAC. Mode 6 operates very similarly to Mode 4. However,
the key difference is that Mode 6 provides return to zero (RZ)
-
DAC output. Mode 4 provides non-return-to-zero - DAC
outputs. The RZ mode ensures that any difference in the rise
and fall times will not effect the -
DAC INL. However, the
RZ mode halves the dynamic range of the -
DAC outputs
from 0–AVDD down to 0–AVDD/2. For best results, this mode
should be used with a PWM clock divider of four.
If PWM1H was set to 4010H (slightly above one quarter of
FS), then typically P2.7 will be low for three full clocks (3
62 ns), high for half a clock (31 ns) and then low again for half
a clock (31 ns) before repeating itself. Over every 65536 clocks
the PWM will compensate for the fact that the output should be
slightly above one quarter of full scale by leaving the output
high for two half clocks in four every so often.
4MHz
16-BIT
248 s
0
16-BIT
CARRY OUT AT P2.6
PWM0H/L = C000H
PWM1H/L = 4000H
00
1
00
0
LATCH
0
11
1
0
248 s
CARRY OUT AT P2.7
0, 3/4, 1/2, 1/4, 0
Figure 32. PWM Mode 6
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