參數(shù)資料
型號(hào)： ADUC831BSZ-REEL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 40/76頁(yè)
文件大小： 0K
描述： IC MCU 62K FLASH ADC/DAC 52MQFP
標(biāo)準(zhǔn)包裝： 800
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 帶卷 (TR)
配用： EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START
REV. 0
ADuC831
–45–
TIME INTERVAL COUNTER (TIC)
A time interval counter is provided on-chip for counting longer
intervals than the standard 8051 compatible timers are capable
of. The TIC is capable of timeout intervals ranging from 1/128
second to 255 hours. Furthermore, this counter is clocked by
an internal R/C oscillator rather than the external crystal and
has the ability to remain active in power-down mode and time
long power-down intervals. This has obvious applications for
remote battery-powered sensors where regular widely spaced
readings are required. The R/C oscillator is accurate to +10% at
25C. Note: Instructions to the TIC SFRs are also clocked at
32 kHz, sufficient time must be allowed for in user code for
these instructions to execute.
Six SFRs are associated with the time interval counter, TIMECON
being its control register. Depending on the configuration of the
IT0 and IT1 bits in TIMECON, the selected time counter regis-
ter overflow will clock the interval counter. When this counter is
equal to the time interval value loaded in the INTVAL SFR, the
TII bit (TIMECON.2) is set and generates an interrupt if enabled.
If the ADuC831 is in power-down mode, again with TIC inter-
rupt enabled, the TII bit will wake up the device and resume
code execution by vectoring directly to the TIC interrupt service
vector address at 0053H. The TIC-related SFRs are described
below. Note also that the time-base SFRs can be written initially
with the current time, the TIC can then be controlled and
accessed by user software. In effect, this facilitates the imple-
mentation of a real-time clock. A block diagram of the TIC is
shown in Figure 35.
TIMECON
TIC Control Register
SFR Address
A1H
Power-On Default Value
00H
Bit Addressable
No
Table XVI. TIMECON SFR Bit Designations
Bit
Name
Description
7
----
Reserved for Future Use.
6
TFH
Twenty-Four Hour Select Bit.
Set by the user to enable the Hour counter to count from 0 to 23.
Cleared by the user to enable the Hour counter to count from 0 to 255.
5
ITS1
Interval Timebase Selection Bits.
4
ITS0
Written by user to determine the interval counter update rate.
ITS1
ITS0
Interval Timebase
00
1/128 Second
01
Seconds
10
Minutes
11
Hours
3
STI
Single Time Interval Bit.
Set by user to generate a single interval timeout. If set, a timeout will clear the TIEN bit.
Cleared by user to allow the interval counter to be automatically reloaded and start counting
again at each interval timeout.
2
TII
TIC Interrupt Bit.
Set when the 8-bit Interval Counter matches the value in the INTVAL SFR.
Cleared by user software.
1
TIEN
Time Interval Enable Bit.
Set by user to enable the 8-bit time interval counter.
Cleared by user to disable the interval counter.
0
TCEN
Time Clock Enable Bit.
Set by user to enable the time clock to the time interval counters.
Cleared by user to disable the clock to the time interval counters and reset the time interval SFRs
to the last value written to them by the user. The time registers (HTHSEC, SEC, MIN, and HOUR)
can be written while TCEN is low.
8-BIT
PRESCALER
HUNDREDTHS COUNTER
HTHSEC
SECOND COUNTER
SEC
MINUTE COUNTER
MIN
HOUR COUNTER
HOUR
TIEN
INTERVAL TIMEOUT
TIME INTERVAL COUNTER INTERRUPT
8-BIT
INTERVAL COUNTER
TIME INTERVAL
INTVAL
INTERVAL
TIMEBASE
SELECTION
MUX
TCEN
32kHz INTERNAL R/C OSC.
ITS0, 1
COMPARE
COUNT = INTVAL?
Figure 35. TIC, Simplified Block Diagram
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