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| 型號： | ADUC831BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標準包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START |
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REV. 0
–22–
ADuC831
Driving the A/D Converter
The ADC incorporates a successive approximation (SAR) archi-
tecture involving a charge-sampled input stage. Figure 9 shows
the equivalent circuit of the analog input section. Each ADC
conversion is divided into two distinct phases as defined by the
position of the switches in Figure 9. During the sampling phase
(with SW1 and SW2 in the “track” position) a charge propor-
tional to the voltage on the analog input is developed across the
input sampling capacitor. During the conversion phase (with
both switches in the “hold” position) the capacitor DAC is
adjusted via internal SAR logic until the voltage on node A is
zero, indicating that the sampled charge on the input capacitor is
balanced out by the charge being output by the capacitor DAC.
The digital value finally contained in the SAR is then latched out
as the result of the ADC conversion. Control of the SAR, and
timing of acquisition and sampling modes, is handled auto-
matically by built-in ADC control logic. Acquisition and
conversion times are also fully configurable under user control.
CAPACITOR
DAC
COMPARATOR
VREF
AGND
DAC1
DAC0
TEMPERATURE MONITOR
AIN7
AIN0
32pF
AGND
ADuC831
NODE A
sw1
sw2
TRACK
HOLD
200
Figure 9. Internal ADC Structure
Note that whenever a new input channel is selected, a residual
charge from the 32 pF sampling capacitor places a transient on
the newly selected input. The signal source must be capable of
recovering from this transient before the sampling switches click
into “hold” mode. Delays can be inserted in software (between
channel selection and conversion request) to account for input
stage settling, but a hardware solution will alleviate this burden
from the software design task and will ultimately result in a
cleaner system implementation. One hardware solution would
be to choose a very fast settling op amp to drive each analog
input. Such an op amp would need to fully settle from a small
signal transient in less than 300 ns in order to guarantee adequate
settling under all software configurations. A better solution, recom-
mended for use with any amplifier, is shown in Figure 10.
Though at first glance the circuit in Figure 10 may look like a
simple antialiasing filter, it actually serves no such purpose since its
corner frequency is well above the Nyquist frequency, even at a
200 kHz sample rate. Though the R/C does helps to reject some
incoming high-frequency noise, its primary function is to ensure
that the transient demands of the ADC input stage are met. It
AIN0
ADuC831
10
0.1 F
Figure 10. Buffering Analog Inputs
does so by providing a capacitive bank from which the 32 pF
sampling capacitor can draw its charge. Its voltage will not
change by more than one count (1/4096) of the 12-bit trans-
fer function when the 32 pF charge from a previous channel
is dumped onto it. A larger capacitor can be used if desired,
but not a larger resistor (for reasons described below).
The Schottky diodes in Figure 10 may be necessary to limit the
voltage applied to the analog input pin as per the data sheet
absolute maximum ratings. They are not necessary if the op
amp is powered from the same supply as the ADuC831 since
in that case the op amp is unable to generate voltages above
VDD or below ground. An op amp of some kind is necessary
unless the signal source is very low impedance to begin with.
DC leakage currents at the ADuC831’s analog inputs can
cause measurable dc errors with external source impedances
as little as 100
or so. To ensure accurate ADC operation, keep
the total source impedance at each analog input less than 61
.
The table below illustrates examples of how source impedance
can affect dc accuracy.
Source
Error from 1
AError from 10 A
Impedance
Leakage Current
61
61
V = 0.1 LSB
610
V = 1 LSB
610
610
V = 1 LSB
6.1 mV = 10 LSB
Although Figure 10 shows the op amp operating at a gain of 1,
you can, of course, configure it for any gain needed. Also, you
can just as easily use an instrumentation amplifier in its place to
condition differential signals. Use any modern amplifier that is
capable of delivering the signal (0 to VREF) with minimal satura-
tion. Some single-supply rail-to-rail op amps that are useful for
this purpose include, but are certainly not limited to, the ones
given in Table VI. Check Analog Devices literature (CD ROM
data book, and so on) for details on these and other op amps
and instrumentation amps.
Table VI. Some Single-Supply Op Amps
Op Amp Model
Characteristics
OP281/OP481
Micropower
OP191/OP291/OP491
I/O Good up to VDD, Low Cost
OP196/OP296/OP496
I/O to VDD, Micropower, Low Cost
OP183/OP283
High Gain-Bandwidth Product
OP162/OP262/OP462
High GBP, Micro Package
AD820/AD822/AD824
FET Input, Low Cost
AD823
FET Input, High GBP
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