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| 型號： | ADUC831BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START |
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REV. 0
ADuC831
–41–
The main features of the MicroConverter I
2C interface are:
Only two bus lines are required; a serial data line (SDATA)
and a serial clock line (SCLOCK).
An I2C master can communicate with multiple slave devices.
Because each slave device has a unique 7-bit address, single
master/slave relationships can exist at all times even in
a multislave environment (Figure 34).
On-Chip filtering rejects <50 ns spikes on the SDATA and
the SCLOCK lines to preserve data integrity.
DVDD
I2C
MASTER
I2C
SLAVE #1
I2C
SLAVE #2
Figure 34. Typical I 2C System
Software Master Mode
The ADuC831 can be used as an I
2C master device by configur-
ing the I
2C peripheral in master mode and writing software to
output the data bit by bit. This is referred to as a software master.
Master mode is enabled by setting the I2CM bit in the I2CCON
register.
To transmit data on the SDATA line, MDE must be set to
enable the output driver on the SDATA pin. If MDE is set, then
the SDATA pin will be pulled high or low depending on
whether the MDO bit is set or cleared. MCO controls the
SCLOCK pin and is always configured as an output in master
mode. In master mode the SCLOCK pin will be pulled high or
low depending on the whether MCO is set or cleared.
To receive data, MDE must be cleared to disable the output
driver on SDATA. Software must provide the clocks by toggling
the MCO bit and read the SDATA pin via the MDI bit. If MDE
is cleared MDI can be used to read the SDATA pin. The value of
the SDATA pin is latched into MDI on a rising edge of SCLOCK.
MDI is set if the SDATA pin was high on the last rising edge of
SCLOCK. MDI is cleared if the SDATA pin was low on the last
rising edge of SCLOCK.
Software must control MDO, MCO, and MDE appropriately to
generate the START condition, slave address, acknowledge bits,
data bytes, and STOP conditions appropriately. These functions
are provided in technical note uC001.
Hardware Slave Mode
After reset the ADuC831 defaults to hardware slave mode. The
I
2C interface is enabled by clearing the SPE bit in SPICON.
Slave mode is enabled by clearing the I2CM bit in I2CCON.
The ADuC831 has a full hardware slave. In slave mode the I
2C
address is stored in the I2CADD register. Data received or to be
transmitted is stored in the I2CDAT register.
Once enabled in I2C slave mode the slave controller waits for a
START condition. If the ADuC831 detects a valid start condi-
tion, followed by a valid address, followed by the R/
W bit, the
I2CI interrupt bit will get set by the hardware automatically.
The I2C peripheral will only generate a core interrupt if the user
has preconfigured the I2C interrupt enable bit in the IEIP2 SFR
as well as the global interrupt bit EA in the IE SFR.
; Enabling I2C Interrupts for the ADuC831
MOV
IEIP2,#01H
; enable I2C interrupt
SETB EA
On the ADuC831 an autoclear of the I2CI bit is implemented
so this bit is cleared automatically on a read or write access to
the I2CDAT SFR.
MOV
I2CDAT, A
; I2CI auto cleared
MOV
A, I2CDAT
; I2CI auto cleared
If for any reason the user tries to clear the interrupt more than
once, i.e., access the data SFR more than once per interrupt
then the I2C controller will halt. The interface will then have to
be reset using the I2CRS bit.
The user can choose to poll the I2CI bit or enable the interrupt.
In the case of the interrupt, the PC counter will vector to
003BH at the end of each complete byte. For the first byte
when the user gets to the I2CI ISR, the 7-bit address and the
R/
W bit will appear in the I2CDAT SFR.
The I2CTX bit contains the R/
W bit sent from the master. If
I2CTX is set then the master would like to receive a byte.
Thus the slave will transmit data by writing to the I2CDAT
register. If I2CTX is cleared, the master would like to transmit
a byte. Therefore, the slave will receive a serial byte. Software
can interrogate the state of I2CTX to determine whether it
should write to or read from I2CDAT.
Once the ADuC831 has received a valid address, hardware will
hold SCLOCK low until the I2CI bit is cleared by software.
This allows the master to wait for the slave to be ready before
transmitting the clocks for the next byte.
The I2CI interrupt bit will be set every time a complete data
byte is received or transmitted, provided it is followed by a valid
ACK. If the byte is followed by a NACK an interrupt is NOT
generated. The ADuC831 will continue to issue interrupts for
each complete data byte transferred until a STOP condition is
received or the interface is reset.
When a STOP condition is received, the interface will reset to a
state where it is waiting to be addressed (idle). Similarly, if the
interface receives a NACK at the end of a sequence it also returns
to the default idle state. The I2CRS bit can be used to reset the
I
2C interface. This bit can be used to force the interface back to
the default idle state.
It should be noted that there is no way (in hardware) to distinguish
between an interrupt generated by a received START + valid
address and an interrupt generated by a received data byte. User
software must be used to distinguish between these interrupts.
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