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| 型號： | ADUC7023BCPZ62I-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 88/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 62KB FLASH 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | I²C，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC7023
| Page 89 of 96
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of the
ADuC7023-based designs to achieve optimum performance
from the ADCs and DACs.
Although the parts have separate pins for analog and digital ground
(AGND and DGND), the user must not tie these to two separate
ground planes unless the two ground planes are connected very
close to the part. This is illustrated in the simplified example
shown in Figure 50a. In systems where digital and analog ground
planes are connected together somewhere else (at the system
power supply, for example), the planes cannot be reconnected
near the part because a ground loop would result. In these cases, tie
all the ADuC7023 AGND and DGND pins to the analog ground
plane, as illustrated in Figure 50b. In systems with only one ground
plane, ensure that the digital and analog components are physically
separated onto separate halves of the board so that digital return
currents do not flow near analog circuitry (and vice versa).
The ADuC7023 can then be placed between the digital and
analog sections, as illustrated in Figure 50c.
08675-
044
a.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
b.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
c.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
DGND
Figure 50. System Grounding Schemes
In all of these scenarios, and in more complicated real-life
applications, users should pay particular attention to the flow of
current from the supplies and back to ground. Make sure the return
paths for all currents are as close as possible to the paths the
currents took to reach their destinations.
For example, do not power components on the analog side (as
currents from IOVDD to flow through AGND. Avoid digital
currents flowing under analog circuitry, which can occur if a
noisy digital chip is placed on the left half of the board (shown
in Figure 50c). If possible, avoid large discontinuities in the
ground plane(s) such as those formed by a long trace on the same
layer, because they force return signals to travel a longer path.
In addition, make all connections to the ground plane directly,
with little or no trace separating the pin from its via to ground.
When connecting fast logic signals (rise/fall time < 5 ns) to any of
the ADuC7023 digital inputs, add a series resistor to each
relevant line to keep rise and fall times longer than 5 ns at the
input pins of the part. A value of 100 or 200 is usually
sufficient enough to prevent high speed signals from coupling
capacitively into the part and affecting the accuracy of ADC
conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7023 can be generated by the
internal PLL or by an external clock input. To use the internal
PLL, connect a 32.768 kHz parallel resonant crystal between
XCLKI and XCLKO, and connect a capacitor from each pin to
ground, as shown in Figure 51. The crystal allows the PLL to lock
correctly to give a frequency of 41.78 MHz. If no external crystal
is present, the internal oscillator is used to give a typical
frequency of 41.78 MHz ± 3%.
08675-
045
ADuC7023
TO
INTERNAL
PLL
12pF
XCLKI
32.768kHz
12pF
XCLKO
Figure 51. External Parallel Resonant Crystal Connections
To use an external source clock input instead of the PLL (see
Figure 52), Bit 1 and Bit 0 of PLLCON must be modified. The
external clock uses P1.1 and XCLK.
08675-
046
ADuC7023
TO
FREQUENCY
DIVIDER
XCLKO
XCLKI
XCLK
EXTERNAL
CLOCK
SOURCE
Figure 52. Connecting an External Clock Source
Using an external clock source, the ADuC7023 specified
operational clock speed range is 50 kHz to 44 MHz ± 1%, which
ensures correct operation of the analog peripherals and Flash/EE.
Rev. E
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