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| 型號： | ADUC7023BCPZ62I-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 82/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 62KB FLASH 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | I²C，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC7023
| Page 83 of 96
IRQCLRE Register
Name:
IRQCLRE
Address:
0xFFFF0038
Default value: 0x00000000
Access:
Read and write
Table 100. IRQCLRE MMR Bit Designations
Bit
Name
Description
31 to
21
Reserved
These bits are reserved and should not be
written to.
20
PLA1CLRI
A 1 must be written to this bit in the PLA IRQ1
interrupt service routine to clear an edge
triggered PLA IRQ1 interrupt.
19
IRQ3CLRI
A 1 must be written to this bit in the external
IRQ3 interrupt service routine to clear an edge
triggered IRQ3 interrupt.
18
IRQ2CLRI
A 1 must be written to this bit in the external
IRQ2 interrupt service routine to clear an edge
triggered IRQ2 interrupt.
17
PLA0CLRI
A 1 must be written to this bit in the PLA IRQ0
interrupt service routine to clear an edge
triggered PLA IRQ0 interrupt.
16
IRQ1CLRI
A 1 must be written to this bit in the external
IRQ1 interrupt service routine to clear an edge
triggered IRQ1 interrupt.
15 to
14
Reserved
These bits are reserved and should not be
written to.
13
IRQ0CLRI
A 1 must be written to this bit in the external
IRQ0 interrupt service routine to clear an edge
triggered IRQ0 interrupt.
12 to
0
Reserved
These bits are reserved and should not be
written to.
TIMERS
The ADuC7023 has three general-purpose timer/counters: Timer0,
Timer1, and Timer2 or Watchdog Timer.
These three timers in their normal mode of operation can be
either free-running or periodic.
In free-running mode, the counter decreases from the maximum
value until zero scale and starts again at the minimum value. (It
also increases from the minimum value until full scale and starts
again at the maximum value.)
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero/full scale and
starts again at the value stored in the load register.
The timer interval is calculated as follows.
If the timer is set to count down,
(
)
Clock
Source
Prescaler
TxLD
Interval
×
=
If the timer is set to count up,
(
)
Clock
Source
Prescaler
xLD
FullScale
Interval
×
=
T
-
The value of a counter can be read at any time by accessing its
value register (TxVAL). When a timer is being clocked from a
clock other than core clock, an incorrect value may be read (due
to asynchronous clock system). In this configuration, TxVAL
should always be read twice. If the two readings are different, it
should be read a third time to get the correct value.
Timers are started by writing in the control register of the
corresponding timer (TxCON).
In normal mode, an IRQ is generated each time the value of the
counter reaches zero when counting down. It is also generated
each time the counter value reaches full scale when counting up.
An IRQ can be cleared by writing any value to clear the register
of that particular timer (TxCLRI).
When using an asynchronous clock-to-clock timer, the interrupt in
the timer block can take more time to clear than the time it takes
for the code in the interrupt routine to execute. Ensure that the
interrupt signal is cleared before leaving the interrupt service
routine. This can be done by checking the IRQSTA MMR.
Hours, Minutes, Seconds, and 1/128 Format
To use the timer in hours, minutes, seconds,and hundreds
format, select the 32768 kHz clock and a prescaler of 256. The
hundreds field does not represent milliseconds but 1/128 of a
seconds (256/32,768). The bits representing the hour, minute,
and second are not consecutive in the register. This arrangement
applies to T1LD and T1VAL when using the Hr:Min:Sec:hundreds
format as set in T1CON[5:4]. See Table 101 for more details.
Table 101. Hours, Minutes, Seconds, and Hundreds Format
Bit
Value
Description
31:24
0 to 23 or 0 to 255
Hours
23:22
0
Reserved
21:16
0 to 59
Minutes
15:14
0
Reserved
13:8
0 to 59
Seconds
7
0
Reserved
6:0
0 to 127
1/128 of second
Timer0 (RTOS Timer)
Timer0 is a general-purpose, 16-bit timer (count-down) with a
programmable prescaler (see Figure 42). The prescaler source is
the core clock frequency (HCLK) and can be scaled by factors
of 1, 16, or 256.
Timer0 can be used to start ADC conversions as shown in the
block diagram in Figure 42.
08675-
036
32.768kHz
OSCILLATOR
UCLK
HCLK
PRESCALER
/1, 16, OR 256
16-BIT
DOWN
COUNTER
16-BIT
LOAD
TIMER0
VALUE
TIMER0 IRQ
ADC CONVERSION
Figure 42. Timer0 Block Diagram
Rev. E
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