參數(shù)資料
型號: ADUC7023BCPZ62I-RL
廠商: Analog Devices Inc
文件頁數(shù): 17/96頁
文件大?。?/td> 0K
描述: IC MCU 12BIT 62KB FLASH 32LFCSP
標(biāo)準(zhǔn)包裝: 5,000
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 44MHz
連通性: I²C,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 32
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 32-WFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
ADuC7023
Data Sheet
| Page 24 of 96
Table 10. IRQ Address Base = 0xFFFF0000
Address
Name
Byte
Access Type
Default Value
Description
0x0000
IRQSTA
4
R
0x00000000
Active IRQ source.
0x0004
IRQSIG
4
R
Current state of all IRQ sources (enabled and disabled).
0x0008
IRQEN
4
R/W
0x00000000
Enabled IRQ sources.
0x000C
IRQCLR
4
W
MMR to disable IRQ sources.
0x0010
SWICFG
4
W
Software interrupt configuration MMR.
0x0014
IRQBASE
4
R/W
0x00000000
Base address of all vectors. Points to start of a 64-byte memory block
which can contain up to 32 pointers to separate subroutine handlers.
0x001C
IRQVEC
4
R
0x00000000
This register contains the subroutine address for the currently active IRQ
source.
0x0020
IRQP0
4
R/W
0x00000000
This register contains the interrupt priority setting for Interrupt Source 1
to Interrupt Source 7. An interrupt can have a priority setting of 0 to 7.
0x0024
IRQP1
4
R/W
0x00000000
This register contains the interrupt priority setting for Interrupt Source 8
to Interrupt Source 15.
0x0028
IRQP2
4
R/W
0x00000000
This register contains the interrupt priority setting for Interrupt Source 16 to
Interrupt Source 21.
0x002C
RESERVE
D
4
R/W
0x00000000
Reserved.
0x0030
IRQCONN
4
R/W
0x00000000
Used to enable IRQ and FIQ interrupt nesting.
0x0034
IRQCONE
4
R/W
0x00000000
This register configures the external interrupt sources as rising edge,
falling edge, or level triggered.
0x0038
IRQCLRE
4
R/W
0x00000000
Used to clear an edge level triggered interrupt source.
0x003C
IRQSTAN
4
R/W
0x00000000
This register indicates the priority level of an interrupt that has just
caused an interrupt exception.
0x0100
FIQSTA
4
R
0x00000000
Active FIQ source.
0x0104
FIQSIG
4
R
Current state of all FIQ sources (enabled and disabled).
0x0108
FIQEN
4
R/W
0x00000000
Enabled FIQ sources.
0x010C
FIQCLR
4
W
MMR to disable FIQ sources.
0x011C
FIQVEC
4
R
0x00000000
FIQ interrupt vector.
0x013C
FIQSTAN
4
RW
0x00000000
This register indicates the priority level of an FIQ that has just caused an
FIQ exception.
Table 11. System Control Address Base = 0xFFFF0200
Address
Name
Byte
Access Type
Default Value1
Description
0x0220
1
R/W
0x00
Remap control register.
0x0230
RSTSTA
1
R/W
0x01
RSTSTA status MMR.
0x0234
RSTCLR
1
W
0x00
RSTCLR MMR for clearing RSTSTA register.
0x0248
RSTKEY1
1
W
0xXX
0x76 should be written to this register before writing to RSTCFG.
0x024C
RSTCFG
1
R/W
0x00
This register allows the DAC and GPIO outputs to retain state after a
watchdog or software reset.
0x0250
RSTKEY2
1
W
0xXX
0xB1 should be written to this register after writing to RSTCFG.
1 N/A means not applicable.
2 Updated by kernel.
Rev. E
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